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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622- POS)
S/UNI622-POS
R
DATASHEET
ISSUE 5: JUNE 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
REVISION HISTORY ISSUE 5 DATE June 2000 DETAIL Repositioned Path Trace Buffer block to connect to Tx and Rx path overhead processor. Revised Receive FIFO. Section 10.7 Receive POS Frame Processor (RXFP) Moved Overhead Byte Receive section from Section 10.15 SONET/SDH Section Trade Buffer (SSTB) to 10.14 SONET/SDH Path Trace Buffer (SPTB). Corrected function name errors in Register 0x03: S/UNI-622 POS Clock Monitors. Changed PTCLKI to PTCLK, REFCLKI to REFCLK, RFCLKI to RFCLK, RCLKI to RCLK and TCLKI to TCLK. Added line loopback operation information to RXDINV and TXDINV in Register 0x07: S/UNI-622-POS Miscellaneous Configuration. Rewrote IINVCNT bit functionality for clarity. Register 0x30 (EXTD=1): RPOP Status/Control. Rewrote DOOLI bit functionality to indicate change to DOOLV bit and CRU out of lock conditions in Register 0.5C: CRSI Configuration. Rewrote DOOLE bit funcitonality to indicate change to DOOLV register events in Register 0x5D: CRSI Status. Corrected bit 1 function name in Register 0xD1: WANS Interrupt and Status. Was PHWVALID. Now RPHALGN.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
ISSUE 4
DATE Dec, 1999
DETAIL #1. Modified section 9.5 (UTOPIA and POS-PHY pin description) and section 14.4 (Functional timing) to reflect operation of the RPA signal (Receive POS-PHY L2 operation requires data be qualified by RVAL). #2 DC characteristics update (Section 16) #3 Registers updated with correct defaults and descriptions: Register 0X01, Bit 4 (TFPEN), Defaults To 1, Not 0 Register 0X08, Description Incorrect Register 0X09 Description Incorrect Register 0XC1, Bit 1 (DSCR), Defaults To 1, Not 0 Register 0XC4, Bit 3 (TPAHWM), Defaults To 0, Not 1 New Register 0XFC: Concatenation Status And Enable New Register 0XFD: Concatenation Interrupt Status New Register Bit Required For OC-3 Operation (Register 0X07) Register 0X5E Bit 5 (RTYPE) To Enable LAN Or WAN Performance Register 0X00 Type Bits Incorrect Loss Of Multi-frame Tributary AIS (LOMTUAIS) Bit 2 Incorrectly Stated In Register 0X0D #4 APS pin description modified #5 Documented overflowing Transmit FIFO #6 Updated TFCLK timing specifications, RFCLK timing specifications #7 Diagnostic Loop-back Clarification #8 Bit Error Rate Monitor Table Update #9 Receive Data Requires 3 RFCLK Cycles Before Becoming Valid (Utopia Level 3 Only) #10 TPAHWM Upper Limit #11 Receive Line AIS Insertion Is Not Gated By ALLONES #12 Large Power Supply Glitch (Beyond Specification) Can Cause Clock Synthesis Unit To Lose Lock To Reference.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
ISSUE 3 2 1
DATE Jan 13, 1999 Dec 12, 1998 Mar 30, 1998
DETAIL Corrected wrong pin number assignments in pin description. General update in preparation for Issue 2 S/UNI-622-POS Updated datasheet
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
CONTENTS
1 FEATURES ..................................................................................................................................... 9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 3 4 5 6 7 8 9 GENERAL ........................................................................................................................ 9 THE SONET RECEIVER ................................................................................................ 10 THE RECEIVE ATM PROCESSOR.................................................................................11 THE RECEIVE POS PROCESSOR ................................................................................11 THE SONET TRANSMITTER......................................................................................... 12 THE TRANSMIT ATM PROCESSOR ............................................................................. 13 THE TRANSMIT POS PROCESSOR............................................................................. 13
APPLICATIONS ............................................................................................................................ 14 REFERENCES ............................................................................................................................. 15 DEFINITIONS ............................................................................................................................... 17 APPLICATION EXAMPLES .......................................................................................................... 20 BLOCK DIAGRAM ........................................................................................................................ 25 DESCRIPTION ............................................................................................................................. 26 PIN DIAGRAM .............................................................................................................................. 29 PIN DESCRIPTION ...................................................................................................................... 30 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 SERIAL LINE SIDE INTERFACE SIGNALS ................................................................... 30 PARALLEL LINE SIDE INTERFACE SIGNALS - CRU AND CSU BYPASS ................... 32 CLOCKS AND ALARMS SIGNALS................................................................................. 35 SECTION AND LINE STATUS DCC PINS...................................................................... 37 ATM (UTOPIA) AND PACKET OVER SONET/SDH (POS) SYSTEM INTERFACE........ 38 MICROPROCESSOR INTERFACE SIGNALS ............................................................... 53 JTAG TEST ACCESS PORT (TAP) SIGNALS................................................................ 55 ANALOG SIGNALS ........................................................................................................ 56 POWER AND GROUND................................................................................................. 57
10
FUNCTIONAL DESCRIPTION...................................................................................................... 63 10.1 10.2 10.3 RECEIVE LINE INTERFACE (CRSI-622)....................................................................... 63 RECEIVE SECTION OVERHEAD PROCESSOR (RSOP)............................................. 65 RECEIVE LINE OVERHEAD PROCESSOR (RLOP) ..................................................... 67
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1
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
10.4
THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR MONITOR (RASE) ........................................................................................................................... 69 RECEIVE PATH OVERHEAD PROCESSOR (RPOP).................................................... 70 RECEIVE ATM CELL PROCESSOR (RXCP)................................................................. 75 RECEIVE POS FRAME PROCESSOR (RXFP) ............................................................. 79 TRANSMIT LINE INTERFACE (CSPI-622) .................................................................... 82 TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP)........................................... 83 TRANSMIT LINE OVERHEAD PROCESSOR (TLOP)................................................... 84 TRANSMIT PATH OVERHEAD PROCESSOR (TPOP) ................................................. 85 TRANSMIT ATM CELL PROCESSOR (TXCP)............................................................... 86 TRANSMIT POS FRAME PROCESSOR (TXFP) ........................................................... 87 SONET/SDH PATH TRACE BUFFER (SPTB)................................................................ 90 SONET/SDH SECTION TRACE BUFFER (SSTB)......................................................... 92 ATM UTOPIA AND PACKET OVER SONET/SDH POS-PHY SYSTEM INTERFACES.. 94 WAN SYNCHRONIZATION CONTROLLER (WANS)..................................................... 98 JTAG TEST ACCESS PORT ........................................................................................ 101 MICROPROCESSOR INTERFACE.............................................................................. 101
10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.19 11 12
NORMAL MODE REGISTER DESCRIPTION ............................................................................ 109 TEST FEATURES DESCRIPTION.............................................................................................. 336 12.1 12.2 MASTER TEST AND TEST CONFIGURATION REGISTERS ...................................... 336 JTAG TEST PORT........................................................................................................ 339
13
OPERATION ............................................................................................................................... 346 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE .......................... 346 ATM CELL DATA STRUCTURE.................................................................................... 352 PACKET OVER SONET/SDH DATA STRUCTURE...................................................... 353 SETTING ATM MODE OF OPERATION....................................................................... 355 SETTING PACKET-OVER-SONET/SDH MODE OF OPERATION .............................. 356 SETTING SONET OR SDH MODE OF OPERATION................................................... 357 BIT ERROR RATE MONITOR ...................................................................................... 358 AUTO ALARM CONTROL CONFIGURATION.............................................................. 359 CLOCKING OPTIONS.................................................................................................. 360 WAN SYNCHRONIZATION (WANS BLOCK) ............................................................... 361
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
13.11 13.12 13.13 13.14 13.15 13.16 13.17 13.18 14
LOOPBACK OPERATION............................................................................................ 361 1+1 APS SUPPORT ..................................................................................................... 365 JTAG SUPPORT .......................................................................................................... 367 BOARD DESIGN RECOMMENDATIONS .................................................................... 372 POWER SUPPLIES ..................................................................................................... 373 INTERFACING TO ECL OR PECL DEVICES............................................................... 376 CLOCK SYNTHESIS AND RECOVERY....................................................................... 378 SYSTEM INTERFACE DLL OPERATION..................................................................... 379
FUNCTIONAL TIMING................................................................................................................ 381 14.1 14.2 14.3 14.4 14.5 14.6 PARALLEL LINE INTERFACE...................................................................................... 381 ATM UTOPIA LEVEL 2 SYSTEM INTERFACE............................................................. 382 ATM UTOPIA LEVEL 3 SYSTEM INTERFACE............................................................. 383 PACKET OVER SONET/SDH (POS) LEVEL 2 SYSTEM INTERFACE ........................ 385 PACKET OVER SONET/SDH (POS) LEVEL 3 SYSTEM INTERFACE ........................ 387 SECTION AND LINE DATA COMMUNICATION CHANNELS ...................................... 389
15 16 17 18
ABSOLUTE MAXIMUM RATINGS .............................................................................................. 392 D.C. CHARACTERISTICS .......................................................................................................... 393 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ............................................ 396 A.C. TIMING CHARACTERISTICS............................................................................................. 400 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 18.10 18.11 SYSTEM RESET TIMING............................................................................................. 400 PARALLEL LINE INTERFACE TIMING ........................................................................ 401 SERIAL LINE INTERFACE TIMING.............................................................................. 403 UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING ....................................................... 404 UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING ....................................................... 408 POS LEVEL 2 SYSTEM INTERFACE TIMING..............................................................411 POS LEVEL 3 SYSTEM INTERFACE TIMING............................................................. 415 TRANSMIT DCC INTERFACE TIMING ........................................................................ 419 RECEIVE DCC INTERFACE TIMING........................................................................... 420 CLOCK AND FRAME PULSE INTERFACE TIMING .................................................... 421 JTAG TEST PORT TIMING .......................................................................................... 422
19 20
ORDERING AND THERMAL INFORMATION............................................................................. 424 MECHANICAL INFORMATION................................................................................................... 425
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3
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
LIST OF FIGURES
FIGURE 1: TYPICAL STS-12C/STM-4-4C ATM (UTOPIA LEVEL 2) SWITCH PORT APPLICATION ....... 21 FIGURE 2: TYPICAL STS-12C/STM-4-4C ATM (UTOPIA LEVEL 3) SWITCH PORT APPLICATION ....... 22 FIGURE 3: TYPICAL STS-12C/STM-4-4C PACKET OVER SONET/SDH (POS-PHY LEVEL 2) APPLICATION ................................................................................................................ 23 FIGURE 4: TYPICAL STS-12C/STM-4-4C PACKET OVER SONET/SDH (POS-PHY LEVEL 3) APPLICATION ................................................................................................................ 24 FIGURE 5: TYPICAL STS-12C/STM-4-4C S/UNI-622-POS JITTER TOLERANCE................................... 64 FIGURE 6: POINTER INTERPRETATION STATE DIAGRAM.................................................................... 71 FIGURE 7: CELL DELINEATION STATE DIAGRAM.................................................................................. 76 FIGURE 8: HCS VERIFICATION STATE DIAGRAM.................................................................................. 78 FIGURE 9: PACKET OVER SONET/SDH FRAME FORMAT .................................................................... 80 FIGURE 10: CRC DECODER .................................................................................................................... 81 FIGURE 11: PACKET OVER SONET/SDH FRAME FORMAT................................................................... 88 FIGURE 12: CRC GENERATOR................................................................................................................ 89 FIGURE 13. WANS PLL BLOCK DIAGRAM .............................................................................................. 99 FIGURE 14: INPUT OBSERVATION CELL (IN_CELL) ............................................................................ 344 FIGURE 15: OUTPUT CELL (OUT_CELL) .............................................................................................. 344 FIGURE 16: BIDIRECTIONAL CELL (IO_CELL) ..................................................................................... 345 FIGURE 17: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ......................................... 345 FIGURE 18: ATM MAPPING INTO THE STS-12C/STM-4-4C SPE ......................................................... 346 FIGURE 19: POS MAPPING INTO THE STS-12C/STM-4-4C SPE......................................................... 347 FIGURE 20: STS-12C/STM-4-4C OVERHEAD ....................................................................................... 347 FIGURE 21: 16-BIT WIDE, 27 WORD ATM CELL STRUCTURE............................................................. 352 FIGURE 22: 8-BIT WIDE, 54 BYTE ATM CELL STRUCTURE................................................................. 353 FIGURE 23: A 63 BYTE PACKET DATA STRUCTURE............................................................................ 354 FIGURE 24: A 63 BYTE PACKET DATA STRUCTURE............................................................................ 355 FIGURE 25: CLOCKING STRUCTURE ................................................................................................... 360 FIGURE 26: LINE LOOPBACK MODE .................................................................................................... 363 FIGURE 27: SERIAL DIAGNOSTIC LOOPBACK MODE......................................................................... 363 FIGURE 28: PARALLEL DIAGNOSTIC LOOPBACK MODE ................................................................... 364
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
FIGURE 29: PATH DIAGNOSTIC LOOPBACK MODE ............................................................................ 364 FIGURE 30: DATA DIAGNOSTIC LOOPBACK MODE ............................................................................ 365 FIGURE 31: 1+1 APS ARCHITECTURE .................................................................................................. 366 FIGURE 32: BOUNDARY SCAN ARCHITECTURE................................................................................. 368 FIGURE 33: TAP CONTROLLER FINITE STATE MACHINE ................................................................... 369 FIGURE 34: POWER SUPPLY FILTERING AND DECOUPLING ............................................................ 375 FIGURE 35: POWER SUPPLY COMPONENT LAYOUT ......................................................................... 376 FIGURE 36: INTERFACING S/UNI-622-POS PECL PINS TO 3.3V DEVICES........................................ 377 FIGURE 37: INTERFACING S/UNI-622-POS PECL PINS TO 5.0V DEVICES........................................ 378 FIGURE 38: IN FRAME DECLARATION TIMING .................................................................................... 381 FIGURE 39: OUT OF FRAME DECLARATION TIMING .......................................................................... 382 FIGURE 40: PARALLEL TRANSMIT INTERFACE TIMING ..................................................................... 382 FIGURE 41: TRANSMIT UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING ............................................ 383 FIGURE 42: RECEIVE UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING............................................... 383 FIGURE 43: TRANSMIT UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING ............................................ 384 FIGURE 44: RECEIVE UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING............................................... 385 FIGURE 45: TRANSMIT POS LEVEL 2 SYSTEM INTERFACE TIMING ................................................. 386 FIGURE 46: RECEIVE POS LEVEL 2 SYSTEM INTERFACE TIMING .................................................... 387 FIGURE 47: TRANSMIT POS LEVEL 3 SYSTEM INTERFACE TIMING .................................................. 388 FIGURE 48: RECEIVE POS LEVEL 3 SYSTEM INTERFACE TIMING .................................................... 389 FIGURE 49: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA EXTRACTION........................ 390 FIGURE 50: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA INSERTION ........................... 391 FIGURE 51: MICROPROCESSOR INTERFACE READ TIMING............................................................. 396 FIGURE 52: MICROPROCESSOR INTERFACE WRITE TIMING ........................................................... 398 FIGURE 53: RSTB TIMING DIAGRAM .................................................................................................... 400 FIGURE 54: TRANSMIT PARALLEL LINE INTERFACE TIMING DIAGRAM........................................... 401 FIGURE 55: RECEIVE PARALLEL LINE INTERFACE TIMING DIAGRAM ............................................. 402 FIGURE 56: RECEIVE SERIAL LINE INTERFACE TIMING DIAGRAM .................................................. 403 FIGURE 57: TRANSMIT UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING DIAGRAM.......................... 405 FIGURE 58: RECEIVE UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING DIAGRAM ............................ 407 FIGURE 59: TRANSMIT UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING DIAGRAM.......................... 409 FIGURE 60: RECEIVE UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING DIAGRAM ............................ 410
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
FIGURE 61: TRANSMIT POS-PHY LEVEL 2 SYSTEM INTERFACE TIMING ........................................ 412 FIGURE 62: RECEIVE POS-PHY LEVEL 2 SYSTEM INTERFACE TIMING........................................... 414 FIGURE 63: TRANSMIT POS-PHY LEVEL 3 SYSTEM INTERFACE TIMING ........................................ 416 FIGURE 64: RECEIVE POS-PHY LEVEL 3 SYSTEM INTERFACE TIMING........................................... 418 FIGURE 65: TRANSMIT DCC INTERFACE TIMING ............................................................................... 419 FIGURE 66: RECEIVE DCC INTERFACE TIMING.................................................................................. 420 FIGURE 67: CLOCK AND FRAME PULSE INTERFACE TIMING ........................................................... 421 FIGURE 68: JTAG PORT INTERFACE TIMING....................................................................................... 422 FIGURE 69: MECHANICAL DRAWING 304 PIN SUPER BALL GRID ARRAY (SBGA) .......................... 425
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6
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
LIST OF TABLES
TABLE 1: POINTER INTERPRETER EVENT (INDICATIONS) DESCRIPTION......................................... 71 TABLE 2: POINTER INTERPRETER TRANSITION DESCRIPTION ......................................................... 73 TABLE 3: HDLC BYTE SEQUENCES........................................................................................................ 80 TABLE 4: HDLC BYTE SEQUENCES........................................................................................................ 90 TABLE 5: OBR MISMATCH MECHANISM................................................................................................. 92 TABLE 6: REGISTER MEMORY MAP ..................................................................................................... 101 TABLE 7: RECEIVE INITIATION LEVEL VALUES ................................................................................... 275 TABLE 8: TRANSMIT INITIATION LEVEL VALUES................................................................................. 294 TABLE 9: INTER PACKET GAPING VALUES.......................................................................................... 295 TABLE 10: TEST MODE REGISTER MEMORY MAP ............................................................................. 336 TABLE 11: INSTRUCTION REGISTER (LENGTH - 3 BITS).................................................................... 339 TABLE 12: S/UNI-622-POS IDENTIFICATION REGISTER ..................................................................... 339 TABLE 13: S/UNI-622-POS BOUNDARY SCAN REGISTER .................................................................. 339 TABLE 14: SETTINGS FOR SONET OR SDH OPERATION................................................................... 357 TABLE 15: RECOMMENDED BERM SETTINGS .................................................................................... 359 TABLE 16: PATH RDI AND EXTENDED RDI REGISTER SETTINGS ..................................................... 359 TABLE 17: 1+1 APS REGISTER 0X06 SETTINGS.................................................................................. 367 TABLE 18: ABSOLUTE MAXIMUM RATINGS ......................................................................................... 392 TABLE 19: D.C CHARACTERISTICS ...................................................................................................... 393 TABLE 20: MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 51) ....................................... 396 TABLE 21: MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 52) ..................................... 398 TABLE 22: RSTB TIMING (FIGURE 53) .................................................................................................. 400 TABLE 23: TRANSMIT PARALLEL LINE INTERFACE TIMING (FIGURE 54) ......................................... 401 TABLE 24: RECEIVE PARALLEL LINE INTERFACE TIMING (FIGURE 55) ........................................... 402 TABLE 25: RECEIVE SERIAL LINE INTERFACE TIMING (FIGURE 56)................................................. 403 TABLE 26: TRANSMIT UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 57) ........................ 404 TABLE 27: RECEIVE UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 58) .......................... 406 TABLE 28: TRANSMIT UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 59) ........................ 408 TABLE 29: RECEIVE UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 60) .......................... 410 TABLE 30: TRANSMIT POS-PHY LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 61) ......................411
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
TABLE 31: RECEIVE POS-PHY LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 62) ....................... 413 TABLE 32: TRANSMIT POS-PHY LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 63) ..................... 415 TABLE 33: RECEIVE POS-PHY LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 64) ....................... 417 TABLE 34: TRANSMIT DCC INTERFACE TIMING (FIGURE 65) ............................................................ 419 TABLE 35: RECEIVE DCC INTERFACE TIMING (FIGURE 66) .............................................................. 420 TABLE 36: CLOCK AND FRAME PULSE INTERFACE TIMING (FIGURE 67) ........................................ 421 TABLE 37: JTAG PORT INTERFACE (FIGURE 68)................................................................................. 422 TABLE 38: ORDERING INFORMATION .................................................................................................. 424 TABLE 39: THERMAL INFORMATION..................................................................................................... 424
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
1 1.1
FEATURES General * * * * * Single chip ATM and Packet over SONET/SDH Physical Layer Device operating at 622.08 Mbit/s. Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432. Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615. Processes duplex bit-serial 622.08 Mbit/s STS-12c/STM-4-4c data streams with on-chip clock and data recovery and clock synthesis. Supports a duplex byte-serial 77.76 Mbyte/s STS-12c/STM-4-4c line side interface for use in applications where by-passing clock recovery, clock synthesis, and serializer-deserializer functionality is desired. Supports a byte-serial 19.44 Mbyte/s STS-3c/STM-1 line side interface on the transmit and/or receive interface for use in applications where a 155.52 Mbit/s data rate is desired. Supports clock recovery by-pass for use in applications where external clock recovery is desired. Complies with Bellcore GR-253-CORE (1995 Issues) jitter tolerance, jitter transfer and intrinsic jitter criteria. Provides control circuitry required to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO. Provides UTOPIA Level 2 16-bit wide System Interface (clocked up to 50 MHz) with parity support for ATM applications. Provides UTOPIA Level 3 compatible 8-bit wide System Interface (clocked up to 100 MHz) with parity support for ATM applications. Provides SATURN POS-PHY Level 2 16-bit System Interface (clocked up to 50 MHz) for Packet over SONET/SDH (POS) applications. This system interface is similar to UTOPIA Level 2, but adapted to packet transfer.
*
* * *
* * *
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
* * * * * * * 1.2 * * * * * * * * *
Provides SATURN POS-PHY Level 3 8-bit System Interface (clocked up to 100 MHz) for Packet over SONET/SDH (POS) applications. Provides support functions for a two chip solution for 1+1 APS operation. Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible. Industrial temperature range (-40C to +85C). 304 pin Super BGA package. The SONET Receiver Provides a serial interface at 622.08 Mbit/s with clock and data recovery. Frames to and de-scrambles the received STS-12c/STM-4-4c stream. Optionally frames to and de-scrambles a received STS-3c/STM-1 stream. Interprets the received payload pointer (H1, H2) and extracts the STS-12c/STM4-4c or STS-3c/STM-1 synchronous payload envelope and path overhead. Extracts the data communication channels (D1-D3, D4-D12) and serializes them at 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) for optional external processing. Filters and captures the automatic protection switch channel (APS) bytes in readable registers and detects APS byte failure. Captures and de-bounces the synchronization status (S1) nibble in a readable register. Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors. Extracts the 16-byte or 64-byte section trace (J0/Z0) sequence and the 16-byte or 64-byte path trace (J1) sequence into internal register banks.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
*
Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS-L), line remote defect indication (RDI-L), loss of pointer (LOP), path alarm indication signal (AIS-P), path remote defect indication (RDIP), path extended remote defect indicator (extended RDI-P). Counts received section BIP-8 (B1) errors, received line BIP-96 (B2) errors, line remote error indicates (REI-L), received path BIP-8 (B3) errors and path remote error indications (REI-P) for performance monitoring purposes. The Receive ATM Processor
*
1.3 * * * * * *
Extracts ATM cells from the received STS-12c/STM-4-4c or STS-3c/STM-1 payload using ATM cell delineation. Provides ATM cell payload de-scrambling. Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering. Detects out of cell Delineation (OCD) and loss of cell delineation (LCD) alarms. Counts number of received cells, idle cells, errored cells and dropped cells. Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up to 50 MHz) with parity support to read extracted cells from an internal four-cell FIFO buffer. Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support to read extracted cells from an internal four-cell FIFO buffer. The Receive POS Processor
*
1.4 * * * *
Supports packet based link layer protocols using byte synchronous HDLC framing like PPP, HDLC and Frame Relay. Performs self-synchronous POS data de-scrambling on the received STS12c/STM-4-4c or STS-3c/STM-1 payload using the x43+1 polynomial. Performs flag sequence detection and terminates the received POS frames. Performs frame check sequence (FCS) validation for CRC-CCITT and CRC-32 polynomials.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
* * * *
Performs control escape de-stuffing of the HDLC stream. Detects for packet abort sequence. Checks for minimum and maximum packet lengths. Optionally deletes short packets and marks those exceeding the maximum length as errored. Provides a SATURN POS-PHY Level 2 compliant 16-bit datapath interface (clocked up to 50 MHz) with parity support to read packet data from an internal 256 byte FIFO buffer. Provides a SATURN POS-PHY Level 3 compliant 8-bit datapath interface (clocked up to 100 MHz) with parity support to read packet data from an internal 256 byte FIFO buffer. The SONET Transmitter
*
1.5 * * * * * *
Synthesizes the 622.08 MHz transmit clock from a 77.76 MHz reference. Provides a differential PECL bit-serial interface at 622.08 Mbit/s. Inserts a register programmable path signal label (C2). Generates the transmit payload pointer (H1, H2) and inserts the path overhead. Optionally inserts the 16-byte or 64-byte section trace (J0/Z0) sequence and the 16-byte or 64-byte path trace (J1) sequence from internal register banks. Optionally inserts externally generated data communication channels (D1-D3, D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial stream. Scrambles the transmitted STS-12c/STM-4-4c or STS-3c/STM-1 stream and inserts the framing bytes (A1, A2). Optionally inserts register programmable APS bytes. Provides a byte-serial transmit path data stream allowing two devices to implement 1+1 APS. Inserts path BIP-8 codes (B3), path remote error indications (REI-P), line BIP-96 codes (B2), line remote error indications (REI-L), and section BIP-8 codes (B1) to allow performance monitoring at the far end.
* * * *
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
12
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
* * 1.6 * * * * * 1.7 * * * * * * * * *
Allows forced insertion of all-zeros data (after scrambling) and the corruption of the section, line, or path BIP-8 codes for diagnostic purposes. Inserts ATM cells or POS frames into the transmitted STS-12c/STM-4-4c or STS3c/STM-1 payload. The Transmit ATM Processor Provides idle/unassigned cell insertion. Provides HCS generation/insertion, and ATM cell payload scrambling. Counts number of transmitted and idle cells. Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up to 50 MHz) with parity support for writing cells into an internal four-cell FIFO. Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support for writing cells into an internal four-cell FIFO. The Transmit POS Processor Supports any packet based link layer protocol using byte synchronous HDLC framing like PPP, HDLC and Frame Relay. Performs self-synchronous POS data scrambling using the 1+X43 polynomial. Encapsulates packets within a POS frame. Performs flag sequence insertion. Performs byte stuffing for transparency processing. Performs frame check sequence generation using the CRC-CCITT and CRC-32 polynomials. Aborts packets under the direction of the host or when the FIFO underflows. Provides a SATURN POS-PHY Level 2 compliant 16-bit wide datapath (clocked up to 50 MHz) with parity support to an internal 256 byte FIFO buffer. Provides a SATURN POS-PHY Level 3 compliant 8-bit wide datapath (clocked up to 100 MHz) with parity support to an internal 256 byte FIFO buffer.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
13
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
2
APPLICATIONS * * * * * WAN and Edge ATM switches. LAN switches and hubs. Packet switches and hubs. Routers and Layer 3 Switches Network Interface Cards and Uplinks
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
14
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
3
REFERENCES * * * * * * * * * * ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995. ATM Forum - "UTOPIA, An ATM PHY Interface Specification, Level 2, Version 1", June, 1995. Bell Communications Research - GR-253-CORE "SONET Transport Systems: Common Generic Criteria", Issue 2, December 1995. Bell Communications Research - GR-436-CORE "Digital Network Synchronization Plan", Issue 1 Revision 1, June 1996.. ETS 300 417-1-1, "Generic Functional Requirements for Synchronous Digital Hierarchy (SDH) Equipment", January, 1996. IETF Network Working Group - RFC-2615 "Point to Point Protocol (PPP) over SONET/SDH Specification", May 1994. IETF Network Working Group - RFC-1661 "The Point to Point Protocol (PPP)", July 1994. IETF Network Working Group - RFC-1662 "PPP in HDLC like framing", July 1994. ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of Hierarchical Digital Interfaces", 1991. ITU-T Recommendation G.704 - "General Aspects of Digital Transmission Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995. ITU, Recommendation G.707 - "Network Node Interface For The Synchronous Digital Hierarchy", 1996. ITU Recommendation G781, "Structure of Recommendations on Equipment for the Synchronous Design Hierarchy (SDH)", January 1994. ITU, Recommendation G.783 - "Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks", 1996. ITU Recommendation I.432, "ISDN User Network Interfaces", March 93.
* * * *
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
15
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
* *
PMC-971147 "Saturn Compliant Interface for Packet over SONET Physical Layer and Link Layer Devices, Level 2", January 1998. PMC-980495 "Saturn Compliant Interface for Packet over SONET Physical Layer and Link Layer Devices, Level 3", December 1998.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
16
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
4
DEFINITIONS The following table defines the abbreviations for the S/UNI-622-POS. AIS Alarm Indication Signal APS ASSP ATM BER BIP CBI CMOS CRC CRSI CRU CSPI CSU DCC ECL ERDI ESD FCS FEBE FIFO GFC HCS HDLC LAN LCD LOF Automatic Protection Switching Application Specific Standard Product Asynchronous Transfer Mode Bit Error Rate Byte Interleaved Parity Common Bus Interface Complementary Metal Oxide Semiconductor Cyclic Redundancy Check CRU and Serial-In Parallel-Out Clock Recovery Unit CSU and Parallel-In Serial-Out Clock Synthesis Unit Data Communication Channel Emitter Controlled Logic Enhanced Remote Defect Indication Electrostatic Discharge Frame Check Sequence Far-End Block Error First-In First-Out Generic Flow Control Header Check Sequence High-level Data Link Layer Local Area Network Loss of Cell Delineation Loss of Frame
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
17
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
LOH LOP LOS LOT NC NDF NNI ODL OOF PECL PLL POS PPP PSL PSLM RASE RDI RLOP RPOP RSOP RXCP RXFP SBGA SD SDH SF SOH SONET SPE
Line Overhead Loss of Pointer Loss of Signal Loss of Transition No Connect, indicates an unused pin New Data Flag Network-Network Interface Optical Data Link Out of Frame Pseudo-ECL Phase-Locked Loop Packet Over SONET Point-to-Point Protocol Path Signal Label Path Signal Label Mismatch Receive APS, Synchronization Extractor and Bit Error Monitor Remote Defect Indication Receive Line Overhead Processor Receive Path Overhead Processor Receive Section Overhead Processor Receive ATM Cell Processor Receive POS Frame Processor Super Ball Grid Array Signal Degrade (alarm), Signal Detect (pin) Synchronous Digital Hierarchy Signal Fail Section Overhead Synchronous Optical Network Synchronous Payload Envelope
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
18
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
SPTB SSTB TIM TIU TLOP TOH TPOP TSOP TXCP TXFP UI UNI VCI VCXO VPI WAN XOR
SONET/SDH Path Trace Buffer SONET/SDH Section Trace Buffer Trace Identifier Mismatch Trace Identifier Unstable Transmit Line Overhead Processor Transport Overhead Transmit Path Overhead Processor Transmit Section Overhead Processor Transmit ATM Cell Processor Transmit POS Frame Processor Unit Interval User-Network Interface Virtual Connection Indicator Voltage Controlled Oscillator Virtual Path Indicator Wide Area Network Exclusive OR logic operator
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
19
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
5
APPLICATION EXAMPLES The PM5357 S/UNI-622-POS is applicable to equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ATM Network-Network Interfaces (NNI), as well as Packet over SONET/SDH (POS) interfaces. The POS interface can support several packet based protocols, including the Point-to-Point Protocol (PPP). The S/UNI-622-POS may find application at either end of switch-to-switch links or switch-to-terminal links, both in public network (WAN) and private network (LAN) situations. The S/UNI-622-POS provides a comprehensive feature set as well as full compliance to WAN synchronization requirements. The S/UNI-622-POS performs the mapping of either ATM cells or POS frames into the SONET/SDH STS-12c/STM-4-4c synchronous payload envelope (SPE) and processes applicable SONET/SDH section, line and path overheads. In a typical STS-12c/STM-4-4c ATM application, the S/UNI-622-POS performs clock and data recovery in the receive direction and clock synthesis in the transmit direction of the line interface. The S/UNI-622-POS can also be configured to by-pass the clock recovery, clock synthesis, and serializer/deserializer functions. In this mode, an external clock and data recovery/serial-toparallel converter device is required in the receive direction, and an external serial-to-parallel converter/clock synthesis device is required in the transmit direction. On the system side, the S/UNI-622-POS interfaces directly with ATM layer processors and switching or adaptation functions using a UTOPIA Level 2 compliant 16-bit (clocked up to 50 MHz) or an UTOPIA Level 3 8-bit (clocked up to 100 MHz) synchronous FIFO style interface. An application with a UTOPIA Level 2 system side interface is shown in Figure 1. An application with a UTOPIA Level 3 system side is shown in Figure 2. The initial configuration and ongoing control and monitoring of the S/UNI-622-POS are normally provided via a generic microprocessor interface.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
20
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 1: Typical STS-12c/STM-4-4c ATM (UTOPIA Level 2) Switch Port Application
UTOPIA Level 2 Interface ATM Layer Device TxClk TxEnb TxClav TxSOC TxPrty TxData[15:0] PM5357 S/UNI-622-POS TFCLK TENB TCA TSOC TPRTY TDAT[15:0] RXD+/SD RxClk RxEnb RxClav RxSOC RxPrty RxData[15:0] RFCLK RENB RCA RSOC RPRTY RDAT[15:0] POS_ATMB SYSSEL 0 0 TXD+/Optical Transceiver LIFSEL 0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
21
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 2: Typical STS-12c/STM-4-4c ATM (UTOPIA Level 3) Switch Port Application
UTOPIA Level 3 Interface ATM Layer Device TxClk TxEnb TxClav TxSOC TxPrty TxData[7:0] PM5357 S/UNI-622-POS TFCLK TENB TCA TSOC TPRTY TDAT[7:0] RXD+/SD RxClk RxEnb RxVal RxSOC RxPrty RxData[7:0] RFCLK RENB RVAL RSOC RPRTY RDAT[7:0] POS_ATMB SYSSEL 0 1 TXD+/Optical Transceiver LIFSEL 0
In a typical Packet over SONET/SDH application (i.e. using the PPP protocol) the S/UNI-622-POS performs clock and data recovery in the receive direction and clock synthesis in the transmit direction of the line interface. On the system side, the S/UNI-622-POS interfaces directly with a data link layer processor using a SATURN POS-PHY Level 2 16-bit (clocked up to 50 MHz) or a SATURN POSPHY Level 3 8-bit (clocked up to 100 MHz) synchronous FIFO interface over which packets are transferred. An application with a POS-PHY Level 2 interface is shown in Figure 3. An application with a POS-PHY Level 2 interface is shown in Figure 4. The initial configuration and ongoing control and monitoring of the S/UNI-622-POS are normally provided via a generic microprocessor interface.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
22
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 3: Typical STS-12c/STM-4-4c Packet over SONET/SDH (POS-PHY Level 2) Application
POS-PHY Level 2 Interface Link Layer Device TFCLK TENB TPA TSOP TPRTY TDAT[15:0] TMOD TEOP TERR PM5357 S/UNI-622-POS TFCLK TENB TPA TSOP TPRTY TDAT[15:0] TMOD TEOP TERR RFCLK RENB RPA RSOP RPRTY RDAT[15:0] RMOD REOP RERR RVAL POS_ATMB SYSSEL 1 0 RXD+/SD RFCLK RENB RPA RSOP RPRTY RDAT[15:0] RMOD REOP RERR RVAL TXD+/Optical Transceiver LIFSEL 0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
23
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 4: Typical STS-12c/STM-4-4c Packet over SONET/SDH (POS-PHY Level 3) Application
POS-PHY Level 3 Interface Link Layer Device TFCLK TENB TPA TSOP TPRTY TDAT[7:0] TMOD TEOP TERR PM5357 S/UNI-622-POS TFCLK TENB TPA TSOP TPRTY TDAT[7:0] TMOD TEOP TERR RFCLK RENB RVAL RSOP RPRTY RDAT[7:0] REOP RERR POS_ATMB SYSSEL 1 1 RXD+/SD RFCLK RENB RVAL RSOP RPRTY RDAT[7:0] REOP RERR TXD+/Optical Transceiver LIFSEL 0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
24
POUT[7:0] FPOUT
RBYP PECLV REFCLK+/RXD+/RRCLK+/SD C1, C0 ATP[1] PICLK PIN[7:0] FPIN OOF Section/ Line DCC Extract Rx APS, Sync Status, BERM Rx Line I/F Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor Rx POS Frame Processor Rx ATM Cell Processor
a
a
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 25
6
PMC-1980911
DATASHEET
PRODUCTION S/UNI-622-POS
POS_ATMB
BLOCK DIAGRAM
TSDCLK
SYSSEL
TLDCLK
LIFSEL
TRSTB
TFPO
TCLK
TFPI
TMS
TDO
TCK
TSD
TXD+/TDREF1, TDREF0 ATP[0] Tx Line I/F PTCLK
Section/ Line DCC Insert
TLD
JTAG Test Access Port Tx POS Frame Processor
TDI
TFCLK TENB TCA/TPA
ISSUE 5
Tx Section O/H Processor
Tx Line O/H Processor
Tx Path O/H Processor Tx ATM Cell Processor
TSOC/TSOP UTOPIA ATM /SATURN POS-PHY Level 2 UTOPIA ATM /SATURN POS-PHY Level 3 System Interface TPRTY TDAT[15:0] TMOD TEOP TERR
PMC-Sierra, Inc.
Section Trace Buffer
WAN Synch.
Path Trace Buffer
RFCLK RENB RCA/RPA RSOC/RSOP RPRTY RDAT[15:0 ] RMOD
SATURN USER NETWORK INTERFACE (622-POS)
REOP RERR RVAL
Microprocessor Interface
PM5357 S/UNI-622-POS
RALRM
RFPO
RCLK
RSDCLK
RSD
RLDCLK
RLD
APSP[4:0]
D[7:0]
A[8:0]
ALE
CSB
WRB
RDB
RSTB
INTB
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
7
DESCRIPTION The PM5357 S/UNI-622-POS SATURN User Network Interface is a monolithic integrated circuit that implements SONET/SDH processing, ATM mapping and Packet over SONET/SDH mapping functions at the STS-12c/STM-4-4c 622.08 Mbit/s rate. The S/UNI-622-POS receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. The S/UNI-622-POS can also be configured for clock and data recovery and clock synthesis by-pass where it receives SONET/SDH frames via a byte-serial interface. The S/UNI-622-POS performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path remote error indications (M1, G1) are also accumulated. The S/UNI-622-POS interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload. When used to implement an ATM UNI or NNI, the S/UNI-622-POS frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be optionally dropped. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled and are written to a four-cell FIFO buffer. The received cells are read from the FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and those that are errored and correctable are accumulated independently for performance monitoring purposes. When used to implement packet transmission over a SONET/SDH link, the S/UNI-622-POS extracts Packet over SONET/SDH (POS) frames from the SONET/SDH synchronous payload envelope. Frames are verified for correct construction and size. The control escape characters are removed. The frame check sequence is optionally verified for correctness and the extracted packets are placed in a receive FIFO. The received packets are read from the FIFO through a 16-bit POS-PHY Level 2 (clocked up to 50 MHz) or an 8-bit POS-PHY Level 3 (clocked up to 100 MHz) system side interface. Valid and FCS errored packet counts are provided for performance monitoring. The S/UNI-622-POS Packet over SONET/SDH implementation is flexible enough to support several link layer protocols, including HDLC, PPP and Frame Relay.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
26
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
The S/UNI-622-POS transmits SONET/SDH streams using a bit serial interface. The S/UNI-622-POS can also be configured for clock and data recovery and clock synthesis by-pass where it transmits the SONET/SDH frames via a byteserial interface. The S/UNI-622-POS synthesizes the transmit clock from a 77.76MHz frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity codes (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path remote error indications (M1, G1) are also inserted. The S/UNI-622-POS generates the payload pointer (H1, H2) and inserts the synchronous payload envelope that carries the POS frame payload. The S/UNI-622-POS also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications. When used to implement an ATM UNI or NNI, ATM cells are written to an internal four cell FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one complete cell. The S/UNI-622-POS provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed. When used to implement a Packet over SONET/SDH link, the S/UNI-622-POS inserts POS frames into the SONET/SDH synchronous payload envelope. Packets to be transmitted are written into a 256-byte FIFO through a 16-bit SATURN POS-PHY Level 2 (clocked up to 50 MHz) or an 8-bit SATURN POSPHY Level 3 (clocked up to 100 MHz) system side interface. POS frames are built by inserting the flags, control escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 can be computed and added to the frame. Several counters are provided for performance monitoring. No line rate clocks are required directly by the S/UNI-622-POS as it synthesizes the transmit clock and recovers the receive clock using a 77.76 MHz reference clock. The S/UNI-622-POS outputs a differential PECL line data (TXD+/-). The S/UNI-622-POS also provides a WAN Synchronization controller that can be used to control an external VCXO in order to fully meet Bellcore GR-253-CORE jitter, wander, holdover and stability requirements. The S/UNI-622-POS is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-622-POS also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
27
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
The S/UNI-622-POS is implemented in low power, +3.3 Volt, CMOS technology. It has TTL compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and outputs support 3.3V and 5.0V compatible pseudo-ECL (PECL). The S/UNI-622-POS is packaged in a 304 pin SBGA package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
28
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
8
PIN DIAGRAM The S/UNI-622-POS is available in a 304 pin SBGA package having a body size of 31 mm by 31 mm and a ball pitch of 1.27 mm.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
29
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
9 9.1
PIN DESCRIPTION Serial Line Side Interface Signals Pin Name RBYP Type Input Pin No. E21 Function The receive bypass (RBYP) input disables clock recovery. If RBYP is high, RXD+/- is sampled on the rising edge of RRCLK+/-. If RBYP is low, the receive clock is recovered from the RXD+/- bit stream. Please refer to the Operation section for a discussion of the operating modes. PECLV Input D22 The PECL signal voltage select (PELCV) selects between 3.3V PECL signaling and 5V PECL signaling for the PECL inputs. When PECLV is low, the PECL inputs expect a 5V PECL signal. When PECLV is high, the PECL inputs expect a 3.3V PECL signal. The PECL biasing pins PBIAS should be set to the appropriate voltage to prevent latchup. Please refer to the Operation section for a discussion of PECL interfacing issues. REFCLK+ REFCLKDifferential Y2 PECL AA1 Input The differential reference clock inputs (REFCLK+/-) provides a jitter-free 77.76 MHz reference clock for both the clock recovery and the clock synthesis circuits. REFCLK+/- is not required if the clock recovery and clock synthesis features are not used. When the WAN Synchronization controller is used, REFCLK+/- is supplied using a VCXO. In that application, the transmit direction can be externally looped timed to the line receiver in order to meet wander transfer and holdover requirements. Please refer to the Operation section for a discussion of PECL interfacing issues and reference clocks.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
30
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Pin Name RXD+ RXD-
Type
Pin No.
Function The receive differential data PECL inputs (RXD+/-) contain the NRZ bit serial receive stream. The receive clock is recovered from the RXD+/- bit stream when RBYP is set low. RXD+/- is sampled on the rising edge of RRCLK+/- when RBYP is set high. Please refer to the Operation section for a discussion of PECL interfacing issues.
Differential W1 PECL V2 Input
RRCLK+ RRCLK-
Differential U1 PECL U2 Input
When clock recovery is bypassed (RBYP set high), RRCLK+/- is nominally a 622.08 MHz 50% duty cycle clock and provides timing for the S/UNI-622-POS receive functions. In this case, RXD+/- is sampled on the rising edge of RRCLK+/-. RRCLK+/- is ignored when RBYP is set low. Please refer to the Operation section for a discussion of PECL interfacing issues.
SD
PECL Input
R2
The receive signal detect PECL input (SD) indicates the presence of valid receive signal power from the Optical Physical Medium Dependent Device. A PECL logic high indicates the presence of valid data. A PECL logic low indicates a loss of signal. Please refer to the Operation section for a discussion of PECL interfacing issues
TXD+ TXD-
Differential L2 PECL L1 Output
The transmit differential data PECL outputs (TXD+/-) contain the 622.08 Mbit/s transmit stream. The TXD+/- outputs are driven using the synthesized clock from the CSU-622. Please refer to the Operation section for a discussion of PECL interfacing issues.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
31
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
9.2
Parallel Line Side Interface Signals - CRU and CSU Bypass Pin Name LIFSEL Type Input Pin No. C23 Function The line interface select (LIFSEL) selects between serial and parallel line interface modes of operation. When tied high, the parallel mode is selected bypassing the clock and data recovery, clock synthesis and the serializer/de-serializer functions. When tied low, serial mode is selected, enabling clock and data recovery, clock synthesis and the serializer/de-serializer functions. During this operation, the parallel interface may be used for 1+1 APS operation. See the Operation section for more discussion of 1+1 APS support. PICLK Input AC19 The parallel input clock (PICLK) provides timing for S/UNI-622-POS receive function operation when the device is configured for the parallel interface mode of operation. When the RSOC3 bit is set high, PICLK is a 19.44 MHz nominally 50% duty cycle clock. When the RSOC3 bit is set low, PICLK is a 77.76 MHz nominally 50% duty cycle clock. When parallel operation is not used, PICLK may be used for 1+1 APS operation. See the Operation section for more discussion of 1+1 APS. OOF Output AA18 The out of frame (OOF) signal is high while the S/UNI-622-POS is out of frame. OOF is set low while the S/UNI-622-POS is in-frame. An out of frame declaration occurs when four consecutive errored framing patterns (A1 and A2 bytes) have been received. OOF is intended to enable an upstream framing pattern detector to search for the framing pattern. This alarm indication is also available via register access. OOF is an asynchronous output with a minimum period of one PICLK clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
32
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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SATURN USER NETWORK INTERFACE (622-POS)
Pin Name FPIN
Type Input
Pin No. AB17
Function The active-high framing position input (FPIN) signal indicates the SONET/SDH frame position on the PIN[7:0] bus. In parallel interface operation, the byte on the PIN[7:0] bus indicated by FPIN is the third A2 of the SONET/SDH framing pattern. FPIN is sampled on the rising edge of PICLK. When parallel interface operation is not used, FPIN may be used for 1+1 APS operation. In this mode, FPIN marks the first synchronous payload envelope byte after the J0/Z0 bytes on PIN[7:0]. See the Operation section for more discussion of 1+1 APS.
PIN[0] PIN[1] PIN[2] PIN[3] PIN[4] PIN[5] PIN[6] PIN[7]
Input
AB18 AA17 AB16 AA16 Y16 AC15 AB15 AA15
In parallel interface operation, the data input (PIN[7:0]) bus carries the byte-serial STS-12c/STM-44c or STS-3c/STM-1 stream. PIN[7] is the most significant bit (corresponding to bit 1 of each serial byte, the first bit received). PIN[0] is the least significant bit (corresponding to bit 8 of each serial byte, the last bit received). PIN[7:0] is sampled on the rising edge of PICLK. When parallel interface operation is not used, PIN[7:0] may be used for 1+1 APS operation. In this mode, PIN[7:0] carries the byte-serial STS-12c/STM4-4c transmit path. See the Operation section for more discussion of 1+1 APS.
PTCLK
Input
Y14
The parallel transmit clock (PTCLK) provides timing for S/UNI-622-POS transmit function operation when the device is configured for the parallel interface mode of operation. When TOC3 is low, PTCLK should be a 77.76 MHz nominally 50% duty cycle clock free-running (non gapped) clock. When TOC3 is high, PTCLK should be a 19.44 MHz nominally 50% duty cycle clock.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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SATURN USER NETWORK INTERFACE (622-POS)
Pin Name FPOUT
Type Output
Pin No.
Function
AC14 In parallel interface operation, the parallel outgoing stream frame pulse (FPOUT) marks the frame alignment on the POUT[7:0] bus. FPOUT marks the first synchronous payload envelope byte after the J0/Z0 bytes. FPOUT is updated on the rising edge of PTCLK. When parallel interface operation is not used, FPOUT may be used for 1+1 APS operation. In this mode, FPOUT marks the first synchronous payload envelope byte after the J0/Z0 bytes. FPOUT is updated on the rising edge of TCLK. See the Operation section for more discussion of 1+1 APS.
POUT[0] POUT[1] POUT[2] POUT[3] POUT[4] POUT[5] POUT[6] POUT[7]
Output
AA14 AB14 AC13 AB13 AA13 Y13 AB12 AA12
In parallel interface operation, the parallel outgoing stream, (POUT[7:0]) carries the scrambled STS12c/STM-4-4c or STS-3c/STM-1 stream in byte-serial format. POUT[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). POUT[0] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). POUT[7:0] is updated on the rising edge of PTCLK. When parallel interface operation is not used, POUT[7:0] may be used for 1+1 APS operation. In this mode, POUT[7:0] carries the byte-serial STS12c/STM-4-4c transmit path and updates on the rising edge of TCLK. See the Operation section for more discussion of 1+1 APS.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
9.3
Clocks and Alarms Signals Pin Name RCLK Type Output Pin No. Function
AC20 The receive clock (RCLK) provides a timing reference for the S/UNI-622-POS receive function outputs. RCLK is a 77.76 MHz, 50% duty cycle clock. AB19 The receive frame pulse output (RFPO), when the framing alignment has been found (the OOF register bit is low), is an 8 kHz signal derived from the receive clock RCLK. RFPO pulses high for one RCLK cycle every 9720 RCLK cycles (STS-12c / STM-4-4c). RFPO is updated on the rising edge of RCLK. The receive alarm (RALRM) output indicates the state of the receive framing. RALRM is low if no receive alarms are active. RALRM is optionally high if line AIS (LAIS), path AIS (PAIS), line RDI (LRDI), path RDI (PRDI), enhanced path RDI (PERDI), loss of signal (LOS), loss of frame (LOF), out of frame (OOF), loss of pointer (LOP), loss of pointer concatenation (LOPC/AISC), loss of cell delineation (LCD), signal fail BER (SFBER), signal degrade BER (SDBER), path trace identification mismatch (TIM) or path signal label mismatch (PSLM) is detected . RALRM is an asynchronous output with a minimum period of one RCLK clock.
RFPO
Output
RALRM
Output
AA19
TCLK
Output
B19
The transmit clock (TCLK) provides timing for the S/UNI-622-POS transmit function operation. TCLK is a 77.76 MHz, 50% duty cycle clock. The active-high framing position output (TFPO) signal is an 8 kHz signal derived from the transmit clock TCLK. TFPO pulses high for one TCLK cycle every 9720 TCLK cycles (STS-12c / STM-4-4c). TFPO is updated on the rising edge of TCLK.
TFPO
Output
A20
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Pin Name TFPI
Type Input
Pin No. A21
Function The active high framing position (TFPI) signal is an 8 kHz timing marker for the transmitter. TFPI is used to align the SONET/SDH transport frame generated by the S/UNI-622-POS device to a system reference. TFPI should be brought high for a single TCLK period every 9720 TCLK cycles or a multiple thereof. TFPI must be tied low if such synchronization is not required. TFPI is sampled on the rising edge of TCLK. The APS Port bus (APS[4:0]) is a bi-directional control bus that can be used to implement a 1+1 APS system. When the APSPOE register bit is set low, the APS[4:0] bus is an input. Data on this bus is used by TPOP to generate the path RDI and path FEBE. When the APSPOE register bit is set high, the APS[4:0] bus is an output with data generated by RPOP. APS[0] APS[1] APS[2] APS[3] APS[4] FEBE Clock (576 kHz) FEBE Data RDI[0] (G1 bit 5) RDI[1] (G1 bit 6) RDI[2] (G1 bit 7)
APS[0] APS[1] APS[2] APS[3] APS[4]
I/O
A19 C18 B18 D17 C17
See the Operation section for more discussion of 1+1 APS.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
9.4
Section and Line Status DCC Pins Pin Name RSDCLK Type Output Pin No. AB20 Function The receive section DCC clock (RSDCLK) is a 192 kHz clock used to update the RSD input. RSDCLK is generated by gapping a 216 kHz clock.
RSD
Output
AC21 The receive section DCC (RSD) signal contains the serial section data communications channel (D1, D2 D3) extracted from the incoming stream. RSD is updated on the falling edge of RSDCLK. Y19 The receive line DCC clock (RLDCLK) is a 576 kHz clock used to update the RLD output. RLDCLK is generated by gapping a 2.16 MHz clock. The receive line DCC (RLD) signal contains the serial line data communications channel (D4 - D12) extracted from the incoming stream. RLD is updated on the falling edge of RLDCLK. The transmit section DCC clock (TSDCLK) is a 192 kHz clock used to sample the TSD input. TSDCLK is generated by gapping a 216 kHz clock. The transmit section DCC (TSD) signal contains the serial section data communications channel (D1, D2 D3). When not used, this input should be connected to logic zero. TSD is sampled on the rising edge of TSDCLK. The transmit line DCC clock (TLDCLK) is a 576 kHz clock used to sample the TLD input. TLDCLK is generated by gapping a 2.16 MHz clock. The transmit line DCC (TLD) signal contains the serial line data communications channel (D4 - D12). When not used, this input should be connected to logic zero. TLD is sampled on the rising edge of TLDCLK.
RLDCLK
Output
RLD
Output
AA20
TSDCLK
Output
B20
TSD
Input
C20
TLDCLK
Output
C19
TLD
Input
D19
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
9.5
ATM (UTOPIA) and Packet over SONET/SDH (POS) System Interface Pin Name
POS_ ATMB
Type
Input
Pin No. Y21
Function The physical layer select (POS_ATMB) pin selects between the ATM and Packet over SONET/SDH modes of operation. When tied low, the device implements the ATM physical layer. When tied high, the device implements the Packet over SONET/SDH physical layer. This pin affects SONET/SDH mapping as well as the pin definitions of the system interface bus and may be overridden by software in the RUL3 and TUL3 registers.
SYSSEL
Input
AA23
The system interface select (SYSSEL) pin selects between the 16-bit UTOPIA/POS-PHY Level 2 mode and the 8-bit UTOPIA/POS-PHY Level 3 mode of the system side interfaces for both ATM and Packet over SONET/SDH operation. When tied low, the 16-bit Level 2 mode is enabled. When tied high, the 8-bit Level 3 mode is enabled. This pin setting affects the pin definitions of the system interface bus and may be overridden by software in the RUL3 and TUL3 registers.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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Pin Name
TFCLK
Type
Input
Pin No. M22
Function UTOPIA transmit FIFO write clock (TFCLK) is used to write ATM cells to the four cell transmit FIFO. When in 16-bit Level 2 ATM mode, TFCLK must cycle at a 50 MHz to 40 MHz instantaneous rate, and must be a free running clock (cannot be gapped). When in 8-bit Level 3 ATM mode, TFCLK must cycle at a 100 MHz to 60 MHz instantaneous rate, and must be a free running clock (cannot be gapped). POS-PHY transmit FIFO write clock (TFCLK) is used to write packet data into the 256 byte packet FIFO. When in 16-bit Level 2 POS mode, TFCLK must cycle at a 50 MHz to 40 MHz instantaneous rate, and must be a free running clock (cannot be gapped). When in 8-bit Level 3 POS mode, TFCLK must cycle at a 100 MHz to 60 MHz instantaneous rate, and must be a free running clock (cannot be gapped).
TEOP
Input
E22
The POS-PHY transmit end of packet (TEOP) marks the end of packet on the TDAT bus when configured for packet data. In 16-bit Level 2 POS mode, the TEOP signal marks the last word of a packet on the TDAT[15:0] bus. The TMOD signal indicates how many bytes are in the last word. It is legal to set TSOP high at the same time as TEOP high in order to support one or two byte packets. In 8-bit Level 3 POS mode, the TEOP signal marks the last byte of a packet on the TDAT[7:0] bus. The TMOD signal is ignored in this mode. TEOP is only valid when TENB is simultaneously asserted. TEOP is only used for POS operation and is sampled on the rising edge of TFCLK.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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SATURN USER NETWORK INTERFACE (622-POS)
Pin Name
TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
Type
Input
Pin No. K22 K21 K20 J23 J22 J21 H22 H21 H20 G23 G22 G21 G20 F22 F21 E23
Function The UTOPIA transmit cell data (TDAT[15:0]) bus carries the ATM cell octets that are written to the transmit FIFO. In 16-bit Level 2 ATM mode, the TDAT[15:0] is considered valid only when TENB is simultaneously asserted. In 8-bit Level 3 ATM mode, the TDAT[7:0] bus is considered valid only when TENB is simultaneously asserted. TDAT[15:8] are ignored. TDAT[15:0] is sampled on the rising edge of TFCLK. The POS-PHY transmit packet data (TDAT[15:0]) bus carries the POS packet octets that are written to the transmit FIFO. In 16-bit Level 2 POS mode, the TDAT[15:0] bus is considered valid only when TENB is simultaneously asserted. In 8-bit Level 3 POS mode, the TDAT[7:0] signals is considered valid only when TENB is simultaneously asserted. TDAT[15:8] are ignored. TDAT[15:0] is sampled on the rising edge of TFCLK.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Pin Name
TSOC
Type
Input
Pin No. L21
Function The UTOPIA transmit start of cell (TSOC) signal marks the start of a cell structure on the TDAT bus. In 16-bit Level 2 ATM mode, the first word of the cell structure is present on the TDAT[15:0] bus when TSOC is high. It is not necessary for TSOC to be present for each cell. In 8-bit Level 3 ATM mode, the first byte of the cell structure is present on the TDAT[7:0] bus when TSOC is high. TSOC must be present for each cell. TSOC is considered valid only when TENB is simultaneously asserted. TSOC is sampled on the rising edge of TFCLK.
TSOP
POS-PHY transmit start of packet (TSOP) signal indicates the start of a packet on the TDAT bus. TSOP is required to be present at all instances for proper operation. In 16-bit Level 2 POS mode, TSOP must be set high for the first word of a packet on TDAT[15:0]. In 8-bit Level 3 POS mode, TSOP must be set high during the first byte of the packet on TDAT[7:0]. TSOP is considered valid only when TENB is simultaneously asserted. TSOP is sampled on the rising edge of TFCLK.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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SATURN USER NETWORK INTERFACE (622-POS)
Pin Name
TPRTY
Type
Input
Pin No. L20
Function The UTOPIA transmit bus parity (TPRTY) signal indicates the parity on the TDAT bus. A parity error is indicated by a status bit and a maskable interrupt. Cells with parity errors are inserted in the transmit stream, so the TPRTY input may be unused. In 16-bit Level 2 ATM mode, the TPRTY signal indicates the parity on the TDAT[15:0] bus. Odd or even parity selection is made in the TXCP registers. In 8-bit Level 3 ATM mode, the TPRTY signal indicates the parity on the TDAT[7:0] bus. Odd or even parity selection is made in the TUL3 registers. TPRTY is considered valid only when TENB is simultaneously asserted. TPRTY is sampled on the rising edge of TFCLK. The POS-PHY transmit bus parity (TPRTY) signal indicates the parity on the TDAT bus. A parity error is indicated by a status bit and a maskable interrupt. Packets with parity errors are inserted in the transmit stream, so the TPRTY input may be unused. In 16-bit Level 2 POS mode, the TPRTY signal indicates the parity on the TDAT[15:0] bus. Odd or even parity selection is made in the TXFP registers. In 8-bit Level 3 POS mode, the TPRTY signal indicates the parity on the TDAT[7:0] bus. Odd or even parity selection is made in the TUL3 registers. TPRTY is considered valid only when TENB is simultaneously asserted. TPRTY is sampled on the rising edge of TFCLK.
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Pin Name
TENB
Type
Input
Pin No. L22
Function The UTOPIA transmit write enable (TENB) signal is an active low input which is used to initiate writes to the transmit FIFO's. When TENB is sampled high, the information sampled on the TDAT, TPRTY and TSOC signals are invalid. When TENB is sampled low, the information sampled on the TDAT, TPRTY and TSOC signals are valid and are written into the transmit FIFO. TENB is sampled on the rising edge of TFCLK. The POS-PHY transmit write enable (TENB) signal is an active low input which is used to initiate writes to the transmit FIFO's. When TENB is sampled high, the information sampled on the TDAT, TPRTY, TSOP, TEOP, TMOD and TERR signals are invalid. When TENB is sampled low, the information sampled on the TDAT, TPRTY, TSOP, TEOP, TMOD and TERR signals are valid and are written into the transmit FIFO. TENB is sampled on the rising edge of TFCLK.
TERR
Input
D23
The POS-PHY transmit error (TERR) is used to indicate that the current packet must be aborted. Packets marked with TERR will be appended with the abort sequence (0x7D-0x7E) when transmitted. In 16-bit Level 2 POS mode, TERR should only be asserted during the last word of the packet being transferred on TDAT[15:0]. In 8-bit Level 3 POS mode, TERR should only be asserted during the last byte of the packet being transferred on TDAT[7:0]. TERR is only considered valid when TENB and TEOP are simultaneously asserted. TERR is ignored for ATM modes of operation and is sampled on the rising edge of TFCLK.
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SATURN USER NETWORK INTERFACE (622-POS)
Pin Name
TCA
Type
Output
Pin No. L23
Function The UTOPIA transmit cell available (TCA) signal provides direct status indication of when cell space is available in the transmit FIFO. When set high, TCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written. TCA is set low to either indicate that the transmit FIFO is near full or that the transmit FIFO is full. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells. Note that regardless of what fill level TCA is set to indicate "full" at, the transmit cell processor can store 4 complete cells. In 16-bit Level 2 ATM mode, TCA will transition low one TFCLK cycle after the payload word 19 or 23 (depending of the configuration in TXCP) is sampled on the TDAT[15:0] bus. In 8-bit Level 3 ATM mode, TCA will transition low on the rising edge of TFCLK before the payload byte 45 is sampled on the TDAT[7:0] bus. TCA is updated on the rising edge of TFCLK.
TPA
The POS-PHY transmit packet available (TPA) signal provides direct status indication the fill status of the transmit FIFO. Note that regardless of what fill level TPA is set to indicate "full" at, the transmit packet processor can store 256 bytes of data. When TPA transitions high, it indicates that the transmit FIFO has enough room to store a configurable number of data bytes. This transition level is selected in the TXFP registers. When TPA transitions low, it indicates that the transmit FIFO is either full or near full as specified by the TXFP registers. TPA is updated on the rising edge of TFCLK.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Pin Name
TMOD
Type
Input
Pin No. K23
Function The POS-PHY transmit word modulo (TMOD) signal indicates the size of the current word when configured for packet data in 16-bit Level 2 mode. TMOD is ignored when the system interface is configured for ATM cell data or Level 3 modes. During a packet transfer, every word on TDAT[15:0] must contain two valid bytes of packet data except at the end of the packet where the word is composed of 1 or 2 valid bytes. TMOD is set high to indicate a word with 1 valid byte present on TDAT[15:8]. TMOD must be set low during all other times. TMOD is considered valid only when TENB is simultaneously asserted. TMOD is only used for POS operation and is sampled on the rising edge of TFCLK.
RFCLK
Input
M21
The UTOPIA receive FIFO read clock (RFCLK). RFCLK is used to read ATM cells from the four cell receive FIFO. When in 16-bit Level 2 ATM mode, RFCLK must cycle at a 50 MHz to 40 MHz instantaneous rate, and must be a free running clock (cannot be gapped). When in 8-bit Level 3 ATM mode, RFCLK must cycle at a 100 MHz to 60 MHz instantaneous rate, and must be a free running clock (cannot be gapped). POS-PHY receive FIFO read clock (RFCLK). This signal is used to read packet data from the 256 byte packet FIFO. When in 16-bit Level 2 POS mode, RFCLK must cycle at a 50 MHz to 40 MHz instantaneous rate, and must be a free running clock (cannot be gapped). When in 8-bit Level 3 POS mode, RFCLK must cycle at a 100 MHz to 60 MHz instantaneous rate, and must be a free runnning clock (cannot be gapped).
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Pin Name
RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15]
Type
Output
Pin No. W21 W22 W23 V21 V22 U20 U21 U22 U23 T20 T21 T22 R21 R22 R23 P20
Function UTOPIA receive cell data (RDAT[15:0]) bus carries the ATM cell octets that are read from the receive FIFO. In 16-bit Level 2 ATM mode, RDAT[15:0] is consider valid only when RENB is asserted. RDAT[15:0] is tristated when RENB is sampled high. In 8-bit Level 3 ATM mode, only the RDAT[7:0] signals are valid when RVAL is asserted. RDAT[15:8] contain invalid data. RDAT[15:0] is updated on the rising edge of RFCLK. POS-PHY receive packet data (RDAT[15:0]) bus carries the POS packet octets that are read from the receive FIFO. In 16-bit Level 2 POS mode, RDAT[15:0] is considered valid only when RVAL is asserted. RDAT[15:0] is tri-stated when RENB is sampled high. In 8-bit Level 3 POS mode, only the RDAT[7:0] signals are valid when RVAL is asserted. RDAT[15:8] contain invalid data. RDAT[15:0] is updated on the rising edge of RFCLK.
RMOD
Output
Y23
The POS-PHY receive modulo (RMOD) indicates the number of bytes carried by the RDAT[15:0] bus during the last word of a packet transfer. During a packet transfer every word must be complete except the last word which can be composed of 1 or 2 bytes. RMOD set high indicate a single valid byte in the word present on RDAT[15:8] while RMOD set low indicates two valid bytes in the word. RMOD is tristated when RENB is sampled high. RMOD is only used in 16-bit Level 2 POS operation and is updated on the rising edge of RFCLK.
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Pin Name
RVAL
Type
Output
Pin No. N21
Function The UTOPIA Level 3 receive data valid (RVAL) signal indicates the validity of the receive data signals. When RVAL is high, the receive signals RDAT, RSOC and RPRTY are valid. When RVAL is low, all receive signals are invalid and must be disregarded. In 16-bit Level 2 ATM mode, RVAL is invalid and must be ignored. In 8-bit Level 3 ATM mode, RVAL will be high when valid data is on the RDAT bus. The RVAL will transition low when the FIFO is empty. Once deasserted, RVAL will remain deasserted until a complete ATM cell is written into the receive FIFO. RVAL is updated on the rising edge of RFCLK. The POS-PHY receive data valid (RVAL) signal indicates the validity of the receive data signals. When RVAL is high, the receive signals RDAT, RSOP, REOP, RMOD, RPRTY and RERR are valid. When RVAL is low, all receive signals are invalid and must be disregarded. In 16-bit Level 2 POS mode, RVAL will transition low on a FIFO empty condition or on an end of packet. Once deasserted, RVAL will remain low until RENB is deasserted. No data will be removed from the receive FIFO while RVAL is held low. RVAL is tristated when RENB is deasserted. See Functional Timing section for more details on using RVAL with RPA. In 8-bit Level 3 mode, RVAL will be high when valid data is on the RDAT bus. RVAL will transition low when the FIFO is empty. RVAL will remain low until a programmable minimum number of bytes exist in the receive FIFO. The threshold is configured using the TXFP registers. RVAL will not assert until RENB is asserted. RVAL is updated on the rising edge of RFCLK.
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Pin Name
RSOC
Type
Output
Pin No. P23
Function The UTOPIA receive start of cell (RSOC) signal marks the start of a cell structure on the RDAT bus. In 16-bit Level 2 ATM mode, the first word of the cell structure is present on the RDAT[15:0] bus when RSOC is high. RSOC is tri-stated when RENB is sampled high. In 8-bit Level 3 ATM mode, the first byte of the cell structure is present on the RDAT[7:0] bus when RSOC is high. RDAT[15:8] are invalid and must be ignored. RSOC is updated on the rising edge of RFCLK.
RSOP
The POS-PHY receive start of packet (RSOP) indicates the start of a packet on the RDAT bus. In 16-bit Level 2 POS mode, RSOP is set high for the first word of a packet on RDAT[15:0]. RSOP is tristated when RENB is sampled high. In 8-bit Level 3 POS mode, RSOP is set high for the first byte of a packet on RDAT[7:0]. RDAT[15:8] are invalid and must be ignored. RSOP is updated on the rising edge of RFCLK
RERR
Output
N22
The POS-PHY receive error (RERR) indicates that the current packet is invalid due to an error such as invalid FCS, excessive length or received abort. In 16-bit Level 2 POS mode, RERR may only assert when REOP is asserted marking the last word of the packet. RERR is tri-stated when RENB is sampled high. In 8-bit Level 3 POS mode, RERR may only assert when REOP is asserted marking the last byte of the packet. RERR is only used in POS mode and is updated on the rising edge of RFCLK.
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Pin Name
RPRTY
Type
Output
Pin No. P21
Function The UTOPIA receive parity (RPRTY) signal indicates the parity of the RDAT bus. When in 16-bit Level 2 ATM mode, the RPRTY signal indicates the parity on the RDAT[15:0] bus. RPRTY is tri-stated when RENB is sampled high. Odd or even parity selection is made in the RXCP registers. When in 8-bit Level 3 ATM mode, the RPRTY signal indicates the parity on the RDAT[7:0] bus. Odd or even parity selection is made in the RUL3 registers. RPRTY is updated on the rising edge of RFCLK. The POS-PHY receive parity (RPRTY indicates the parity of the RDAT bus. When in 16-bit Level 2 POS mode, the RPRTY signal indicates the parity on the RDAT[15:0] bus. RPRTY is tri-stated when RENB is sampled high. Odd or even parity selection is made in the RXFP registers. When in 8-bit Level 3 POS mode, the RPRTY signal indicates the parity on the RDAT[7:0] bus. Odd or even parity selection is made in the RUL3 registers. RPRTY is updated on the rising edge of RFCLK.
REOP
Output
P22
The POS-PHY receive end of packet (REOP) marks the end of packet on the RDAT[15:0] bus. It is legal for RSOP to be high at the same time REOP is high. In 16-bit Level 2 mode, REOP is set high to mark the last word of the packet presented on the RDAT[15:0] bus. When REOP is high, RMOD specifies if the last word has one or two valid bytes of data. REOP is tristated when RENB is deasserted. In 8-bit Level 3 mode, REOP is set high to mark the last byte of the packet presented on the RDAT[7:0] bus. The RMOD signal is not used in this mode. REOP is only used for POS operation and is updated on the rising edge of RFCLK.
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SATURN USER NETWORK INTERFACE (622-POS)
Pin Name
RENB
Type
Input
Pin No. N23
Function The UTOPIA receive read enable (RENB) is used to initiate reads from the receive FIFO. The system may de-assert RENB if it is unable to accept more data. In 16-bit Level 2 ATM mode, a read is not performed and RDAT[15:0], RPRTY and RSOC will tristate when RENB is sampled high. When RENB is sampled low, the word on the RDAT[15:0] bus is read from the receive FIFO and changes to the next value on the next clock cycle. In 8-bit Level 3 ATM mode, a read is not performed and RDAT[7:0] does not change when RENB is sampled high. When RENB is sampled low, the word on the RDAT[7:0] bus is read from the receive FIFO and changes to the next value on the next clock cycle. RENB is sampled on the rising edge of RFCLK.
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Pin Name
Type
Pin No.
Function The POS-PHY receive read enable (RENB) is used to initiate reads from the receive FIFO. During a data transfer, RVAL must be monitored since it will indicate if the data is valid. The system may deassert RENB at any time if it is unable to accept more data. In 16-bit Level 2 POS mode, a read is not performed and RDAT[15:0], RPRTY, RSOP, REOP, RMOD, RVAL and RERR will tristate when RENB is sampled high. When RENB is sampled low, the word on the RDAT[15:0] bus is read from the receive FIFO and changes to the next value in the FIFO on the next clock cycle. During a data transfer, RVAL must be monitored since it will indicate if RDAT[15:0] is valid. Once RVAL deasserts, RENB must eventually be deasserted to reset RVAL. In 8-bit Level 3 POS mode, a read is not performed and RDAT[7:0] does not change when RENB is sampled high. When RENB is sampled low, the word on the RDAT[7:0] bus is read from the receive FIFO and changes to the next value on the next clock cycle. RENB is sampled on the rising edge of RFCLK.
RCA
Output
N20
The UTOPIA receive cell available (RCA) provides direct status indication of when a cell is available in the receive FIFO. In 16-bit Level 2 mode, RCA can be configured to deassert when either zero or four bytes remain in the FIFO. RCA will thus transition low on the rising edge of RFCLK after payload word 24 or 19 is output on the RDAT[15:0] bus depending on the RXCP registers. In 8-bit Level 3 mode, RCA is ignored as the RVAL signal identifies valid data on the RDAT[7:0] bus. RCA is updated on the rising edge of RFCLK.
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SATURN USER NETWORK INTERFACE (622-POS)
Pin Name
RPA
Type
Pin No.
Function The POS-PHY receive packet available (RPA) provides a direct status indication of when a programmable number of bytes of data is available in the receive FIFO. In 16-bit Level 2 mode, the receive FIFO has at least one end of packet or a programmable minimum number of bytes to be read when RPA is high, RPA is otherwise low. The threshold is configured in the RXFP registers. In 16-bit Level 2 mode, the RPA may incorrectly indicate the FIFO fill level is above the high water mark after an end of packet is transferred over RDAT[15:0]. See the Functional Timing section for more details of using RVAL with RPA to prevent data corruption. In 8-bit Level 3 mode, RPA is ignored as the RVAL signal identifies valid data on the RDAT[7:0] bus. RPA is updated on the rising edge of RFCLK.
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9.6
Microprocessor Interface Signals Pin Name CSB Type Input Pin No. C11 Function The active-low chip select (CSB) signal is low during S/UNI-622-POS register accesses. When CSB is high, the RDB and WRB inputs are ignored. When CSB is low, the RDB and WRB are valid. CSB must be high when RSTB is low to properly reset the chip. If CSB is not required (i.e., registers accesses are controlled using the RDB and WRB signals only), CSB must be connected to an inverted version of the RSTB input. RDB Input B11 The active-low read enable (RDB) signal is low during S/UNI-622-POS register read accesses. The S/UNI622-POS drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. The active-low write strobe (WRB) signal is low during a S/UNI-622-POS register write accesses. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. The bi-directional data bus D[7:0] is used during S/UNI-622-POS register read and write accesses.
WRB
Input
A11
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]
I/O
B17 A17 C16 B16 C15 B15 A15 D14 B14 A14 D13 C13 B13 A13 C12 B12
Input
The address bus A[7:0] selects specific registers during S/UNI-622-POS register accesses.
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Pin Name A[8]
Type Input
Pin No. D11
Function The test register select (A[8]) signal selects between normal and test mode register accesses. A[8] is high during test mode register accesses, and is low during normal mode register accesses. A[8] may be tied low. The active-low reset (RSTB) signal provides an asynchronous S/UNI-622-POS reset. RSTB is a Schmitt triggered input with an integral pull-up resistor. CSB must be held high when RSTB is low in order to properly reset this chip.
RSTB
Input
B10
ALE
Input
A10
The address latch enable (ALE) is active-high and latches the address bus A[8:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-622-POS to interface to a multiplexed address/data bus. ALE has an integral pull-up resistor. The active-low interrupt (INTB) signal is set low when a S/UNI-622-POS interrupt source is active and that source is unmasked. The S/UNI-622-POS may be enabled to report many alarms or events via interrupts. Examples of interrupt sources are loss of signal (LOS), loss of frame (LOF), line AIS, line remote defect indication (LRDI) detect, loss of pointer (LOP), path AIS, path remote defect indication and others. INTB is tri-stated when the all enabled interrupt sources are acknowledged via an appropriate register access. INTB is an open drain output.
INTB
Output
C14
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9.7
JTAG Test Access Port (TAP) Signals Pin Name TCK Type Input Pin No. A9 Function The test clock (TCK) signal provides clock timing for test operations that are carried out using the IEEE P1149.1 test access port. The test mode select (TMS) signal controls the test operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor. The test data input (TDI) signal carries test data into the S/UNI-622-POS via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor. The test data output (TDO) signal carries test data out of the S/UNI-622-POS via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when shifting boundary scan data is in progress. The active-low test reset (TRSTB) signal provides an asynchronous S/UNI-622-POS test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor. Note that when not being used, TRSTB may be tied low or connected to the RSTB input.
TMS
Input
D10
TDI
Input
C10
TDO
Output
C9
TRSTB
Input
B9
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9.8
Analog Signals Pin Name TDREF0 TDREF1 Type Analog Pin No. K1 K2 Function The transmit data reference (TDREF0 and TDREF1) analog pins are provided to create calibrated currents for the PECL output transceivers TXD+/-. A 2.00K ohm resistor is connected across the TDREF0 and TDREF1 pins. The analog C1 and C0 pins are provided for applications that must meet SONET/SDH jitter transfer specifications. A 47nF non-polarized capacitor (ceramic 5% X7R or equivalent) is attached across C1 and C0 for these applications. When the capacitor is used, the RTYPE bit in the CRSI must be set to logic one for proper operation. When the capacitor is not used, these pins are left floating and the RTYPE register bit in the CRSI must be set to logic zero for proper operation. ATP[0] ATP[1] Analog E2 F3 The receive and transmit analog test ports (ATP[1:0]). These pins are used for manufacturing testing only and should be tied to analog ground (AVS).
C0 C1
Analog
P3 P2
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9.9
Power and Ground Pin Name VBIAS[0] VBIAS[1] Type Bias Voltage Pin No. W20 E20 Function Digital input biases (VBIAS). When tied to +5V, the VBIAS inputs are used to bias the wells of the digital inputs so that the pads can tolerate up to 5V on their inputs without forward biasing internal ESD protection devices. When VBIAS are tied to +3.3V, the digital inputs will only tolerate 3.3V level voltages. The system interface inputs (RFCLK, RENB, TFCLK, TENB, TDAT[15:0], TMOD, TERR, TSOC/TSOP, TEOP and TPRTY) do not use the bias voltages and are 3.3V tolerant only. PBIAS[0] PBIAS[1] PBIAS[2] PBIAS[3] Bias Voltage W2 V3 R3 M2 PECL input biases (PBIAS). When tied to +5V, the PBIAS inputs are used to bias the wells in the PECL inputs and output so that the pads can tolerate up to 5V without forward biasing internal ESD protection devices. When the PBIAS inputs are tied to +3.3V, the pads will only tolerate 3.3V level voltages. PBIAS[0] PBIAS[1] PBIAS[2] PBIAS[3] REFCLK+/- Input RXD+/- Input RRCLK+/- Input TXD+/- Output
Please see the Operation section for detailed information on PECL interfacing issues. QAVD[0] QAVD[1] Analog Power E3 R1 The quiet power (QAVD) pins for the analog core. QAVD should be connected to well-decoupled analog +3.3V supply. Please see the Operation section for detailed information. QAVS[0] QAVS[1] Analog Ground D1 P4 The quiet ground (QAVS) pins for the analog core. QAVS should be connected to analog ground of the QAVD supply. Please see the Operation section for detailed information.
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Pin Name VDD
Type Digital Power
Pin No.
Function
The digital power (VDD) pins should be connected to A1 a well-decoupled +3.3 V digital power supply. A23 AA3 AA21 AB2 AB22 AC1 AC23 B2 B22 C3 C21 D4 D6 D9 D12 D15 D18 D20 F4 F20 J4 J20 M4 M20 R4 R20 V4 V20 Y4 Y6 Y9 Y12 Y15 Y18 Y20
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Pin Name VSS
Type Digital Ground
Pin No.
Function
The digital ground (VSS) pins should be connected to A2 the digital ground of the digital power supply. A6 A8 A12 A16 A18 A22 AA2 AA22 AB1 AB3 AB21 AB23 AC2 AC6 AC8 AC12 AC16 AC18 AC22 B1 B3 B21 B23 C2 C22 D21 F1 F23 H1 H23 M1 M23 T1 T23 V1 V23
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Pin Name AVD[0] AVD[1] AVD[2] AVD[3] AVD[4] AVD[5] AVD[6] AVD[7] AVD[8] AVD[9] AVD[10] AVD[11] AVD[12] AVD[13] AVD[14] AVD[15] AVD[16] AVD[17] AVD[18] AVD[19] AVD[20] AVD[21] AVD[22] AVD[23] AVD[24] AVD[25] AVD[26] AVD[27] AVD[28] AVD[29] AVD[30] AVD[31]
Type Analog Power
Pin No. D3 D2 F2 H3 J2 K4 K3 L3 P1 T4 U3 Y1 W3 AA4 AC3 AA5 AB5 AC5 AA7 AB7 AA8 AA9 Y10 AC9 AB10 D8 C7 B6 B5 A4 A3 C4
Function The analog power (AVD) pins for the analog core. The AVD pins should be connected through passive filtering networks to a well-decoupled +3.3V analog power supply. Please see the Operation section for detailed information.
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Pin Name AVS[0] AVS[1] AVS[2] AVS[3] AVS[4] AVS[5] AVS[6] AVS[7] AVS[8] AVS[9] AVS[10] AVS[11] AVS[12] AVS[13] AVS[14] AVS[15] AVS[16] AVS[17] AVS[18] AVS[19] AVS[20] AVS[21] AVS[22] AVS[23] AVS[24] AVS[25] AVS[26] AVS[27] AVS[28] AVS[29] AVS[30] AVS[31] AVS[32] AVS[33] AVS[34] AVS[35] AVS[36] AVS[37] AVS[38] AVS[39]
Type Analog Ground
Pin No. E4 C1 G3 H4 G2 G1 H2 J3 J1 L4 M3 N1 N2 N3 N4 T2 T3 U4 W4 Y3 Y5 AB4 AC4 AA6 Y7 AB6 Y8 AC7 AB8 AB9 AA10 AC10 A7 B7 A5 D7 C6 C5 B4 D5
Function The analog ground (AVS) pins for the analog core. The AVS pins should be connected to the analog ground of the analog power supply. Please see the Operation section for detailed information.
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Notes on Pin Description: 1. All S/UNI-622-POS inputs and bi-directional signals present minimum capacitive loading and operate at TTL logic levels except the inputs marked as Analog or differential pseudo-ECL (PECL). 2. The RDAT[15:0], RPRTY, RSOC/RSOP, REOP, RMOD, RERR, RCA/RPA, RVAL, RCLK, RFPO, TCA/TPA, TCLK, TFPO, POUT[7:0], FPOUT and OOF outputs have a 8mA drive capability. The TDO and INTB outputs have a 2mA drive capability. All other digital outputs and bi-directional signals have 4mA drive capability. 3. The system interface inputs RFCLK, RENB, TFCLK, TENB, TDAT[15:0], TMOD, TERR, TSOC/TSOP, TEOP and TPRTY do not use the ESD bias voltages (VBIAS and PBIAS pins) and are 3.3V tolerate only. All other digital inputs (excluding inputs marked Analog), may operate with 5V signalling with appropriate ESD biasing. 4. The differential pseudo-ECL inputs and outputs should be terminated in a passive network and interface at PECL levels as described in the Operation section. 5. It is mandatory that every digital ground pin (VSS) be connected to the printed circuit board ground plane to ensure reliable device operation. 6. It is mandatory that every digital power pin (VDD) be connected to the printed circuit board power plane to ensure reliable device operation. 7. All analog power and ground pins can be sensitive to noise. They must be isolated from the digital power and ground. Care must be taken to correctly decouple these pins. Please refer to the Operation section and the S/UNI622-POS reference design (PMC-981070) for more information. 8. Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible to damage these ESD protection devices or trigger latch up. Please adhere to the recommended power supply sequencing as described in the Operation section of this document.
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10 FUNCTIONAL DESCRIPTION 10.1 Receive Line Interface (CRSI-622) The Receive Line Interface allows direct interface of the S/UNI-622-POS to optical modules (ODLs) or other medium interfaces. This block performs clock and data recovery on the incoming 622.08 Mbit/s data stream and SONET/SDH A1/A2 pattern framing. Clock Recovery The clock recovery unit recovers the clock from the incoming bit serial data stream and is compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery PLL. Under loss of transition conditions, the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes. The clock recovery unit utilizes a 77.76 MHz reference clock. The clock recovery unit provides status bits that indicate whether it is locked to data or the reference and also supports diagnostic loopback and a loss of signal input that squelches normal input data. Initially upon start-up, the PLL locks to the reference clock, REFCLK. When the frequency of the recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data. Once in data lock, the PLL reverts to the reference clock if no data transitions occur in 96 bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock. When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of transition condition. To meet the Bellcore GR253-CORE SONET Network Element free-run accuracy specification, the reference must be within +/-20 ppm. For LAN applications, the REFCLK accuracy may be relaxed to +/-50 ppm. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET/SDH data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance specified for SONET/SDH equipment by GR-253-CORE. The typical jitter tolerance performance of the S/UNI-622-POS is shown in Figure 5 with the GR-253-CORE jitter tolerance specification limits. The jitter tolerance setup used a Hewlett Packard HFCT-5208M single-mode fiber optic transceiver
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with approximately -10 dBm input power. A 47 nF capacitor was connected between the C0 and C1 pins on the device and the RTYPE register bit in CRSI622 was set to logic one. Note that for frequencies below 300Hz, the jitter tolerance is greater than 22 UIpp; 22UIpp is the maximum jitter tolerance of the test equipment. The dip in the jitter tolerance curve between 10 kHz and 30 kHz is due to the clock difference detector. Figure 5: Typical STS-12c/STM-4-4c S/UNI-622-POS Jitter Tolerance
100
10
Jitter Tolerenace [UIpp]
1
0.1 10 100 1000 10000
Jitter Frequency [Hz]
100000
1000000
10000000
Serial to Parallel Converter The Serial to Parallel Converter (SIPO) converts the received bit serial stream to a byte serial stream. The SIPO searches for the initial SONET/SDH framing pattern in the receive stream, and performs serial to parallel conversion on octet boundaries. While out of frame, the CRSI-622 block monitors the bit-serial STS-12c/STM-44c data stream for an occurrence of a A1 byte. The CRSI-622 adjusts its byte alignment of the serial-to-parallel converter when three consecutive A1 bytes followed by three consecutive A2 bytes occur in the data stream. The CRSI
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informs the RSOP Framer block when this framing pattern has been detected to reinitializes the RSOP to the new frame alignment. While in frame, the CRSI-622 maintains the byte alignment of the serial-toparallel converter until RSOP declares out of frame. 10.2 Receive Section Overhead Processor (RSOP) The Receive Section Overhead Processor (RSOP) provides frame synchronization, descrambling, section level alarm and performance monitoring. In addition, it extracts the section data communication channel from the section overhead and provides it serially on output RSD. Framer The Framer Block determines the in-frame/out-of-frame status of the receive stream. While in-frame, the framing bytes (A1, A2) in each frame are compared against the expected pattern. Out-of-frame is declared when four consecutive frames containing one or more framing pattern errors have been received. While out of frame, the CRSI-622 block monitors the bit-serial STS-12c/STM-44c data stream for an occurrence of the framing pattern (A1, A2). The CRSI-622 informs the RSOP Framer block when three A1 bytes followed by three A2 bytes has been detected to reinitializes the frame byte counter to the new alignment. The Framer block declares frame alignment on the next SONET/SDH frame when either all A1 and A2 bytes are seen error-free or when only the first A1 byte and the first four bits of the last A2 byte are seen error-free depending upon the selected framing algorithm. Once in frame, the Framer block monitors the framing pattern sequence and declares out of frame (OOF) when one or more bit errors in each framing pattern are detected for four consecutive frames. Again, depending upon the algorithm either 24 framing bytes are examined for bit errors each frame, or only the first A1 byte and the first four bits of the last A2 byte are examined for bit errors each frame. When the parallel line interface PIN[7:0] is used, upstream circuitry monitors the receive stream for an occurrence of the three A1 bytes followed by three A2 bytes framing pattern while out-of-frame. The upstream circuitry is expected to pulse input FPIN when the third A2 byte has been detected. RSOP monitors the receive data stream on PIN[7:0] for the framing pattern as before. Once in frame, RSOP monitors the framing pattern sequence and sets the OOF pin when one or more bit errors in each framing pattern are detected for four consecutive frames.
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Descramble The Descramble Block utilizes a frame synchronous descrambler to process the receive stream. The generating polynomial is x7 + x6 + 1 and the sequence length is 127. Details of the descrambling operation are provided in the references. Note that the framing bytes (A1 and A2) and the trace/growth bytes (J0/Z0) are not descrambled. A register bit is provided to disable the descrambling operation. Data Link Extract The Data Link Extract Block extracts the section data communication channel (bytes D1, D2, and D3) from the STS-12c/STM-4-4c stream. The extracted bytes are serialized and output on signal RSD at a nominal 192 kbit/s rate. Timing for downstream processing of the data communication channel is provided by the RSDCLK signal that is also output by the Data Link Extract Block. RSDCLK is derived from a 216 kHz clock that is gapped to yield an average frequency of 192 kHz. RSD is updated with timing aligned to RSDCLK. Error Monitor The Error Monitor Block calculates the received section BIP-8 error detection code (B1) based on the scrambled data of the complete STS-12c/STM-4-4c frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 code is compared with the BIP-8 code extracted from the B1 byte of the following frame. Differences indicate that a section level bit error has occurred. Up to 64000 (8 x 8000) bit errors can be detected per second. The Error Monitor Block accumulates these section level bit errors in a 16-bit saturating counter that can be read via the microprocessor interface. Circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that this counter be polled at least once per second so as not to miss bit error events. Loss of Signal The Loss of Signal Block monitors the scrambled data of the receive stream for the absence of 1's or 0's. When 20 3 s of all zeros patterns or all ones patterns are detected, a loss of signal (LOS) is declared. Loss of signal is cleared when two valid framing words are detected and during the intervening time, no loss of signal condition is detected. The LOS signal is optionally reported on the RALRM output pin when enabled by the LOSEN Receive Alarm Control Register bit.
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Loss of Frame The Loss of Frame Block monitors the in-frame / out-of-frame status of the Framer Block. A loss of frame (LOF) is declared when an out-of-frame (OOF) condition persists for 3 ms. The LOF is cleared when an in-frame condition persists for a period of 3 ms. To provide for intermittent out-of-frame (or in-frame) conditions, the 3 ms timer is not reset to zero until an in-frame (or out-of-frame) condition persists for 3 ms. The LOF and OOF signals are optionally reported on the RALRM output pin when enabled by the LOFEB and OOFEN Receive Alarm Control Register bits. 10.3 Receive Line Overhead Processor (RLOP) The Receive Line Overhead Processor (RLOP) provides line level alarm and performance monitoring. In addition, it extracts the line data communication channel from the line overhead and provides it serially on output RLD. Line RDI Detect The Line RDI Detect Block detects the presence of Line Remote Defect Indication (LRDI) in the receive stream. Line RDI is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line RDI is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal is optionally reported on the RALRM output pin when enabled by the LRDIEN Receive Alarm Control Register bit. Line AIS Detect The Line AIS Block detects the presence of a Line Alarm Indication Signal (LAIS) in the receive stream. Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line AIS is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LAIS signal is optionally reported on the RALRM output pin when enabled by the LAISEN Receive Alarm Control Register bit. Data Link Extract Block The Data Link Extract Block extracts the line data communication channel (bytes D4 to D12) from the STS-12c/STM-4-4c stream. The extracted bytes are serialized and output on the RLD output at a nominal 576 kbit/s rate. Timing for downstream processing of the data communication channel is provided by the
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RLDCLK output. RLDLCLK is derived from a 2.16 MHz clock that is gapped to yield an average frequency of 576 kHz. Error Monitor Block The Error Monitor Block calculates the received line BIP-8 error detection codes based on the Line Overhead bytes and synchronous payload envelopes of the STS-12c/STM-4-4c stream. The line BIP-8 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 codes are compared with the BIP-8 codes extracted from the following frame. Any differences indicate that a line layer bit error has occurred. Optionally the RLOP can be configured to count a maximum of only one BIP error per frame. This block also extracts the line FEBE code from the M1 byte. The FEBE code is contained in bits 2 to 8 of the M1 byte, and represents the number of line BIP-8 errors that were detected in the last frame by the far end. The FEBE code value has 97 legal values (0 to 96) for an STS-12c/STM-4-4c stream. Illegal values are interpreted as zero errors. The Error Monitor Block accumulates B2 error events and FEBE events in two 20-bit saturating counters that can be read via the CBI. The contents of these counters may be transferred to internal holding registers by writing to any one of the counter addresses, or by using the TIP register bit feature. During a transfer, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note, these counters should be polled at least once per second to avoid saturation. The B2 error event counters optionally can be configured to accumulate only "word" errors. A B2 word error is defined as the occurrence of one or more B2 bit error events during a frame. The B2 error counter is incremented by one for each frame in which a B2 word error occurs. In addition the FEBE events counters optionally can be configured to accumulate only "word" events. A FEBE word event is defined as the occurrence of one or more FEBE bit events during a frame. The FEBE event counter is incremented by one for each frame in which a FEBE event occurs. If the extracted FEBE value is in the range 1 to 4 the FEBE event counter will be incremented for each and every FEBE bit. If the extracted FEBE value is greater than 4 the FEBE event counter will be incremented by 4.
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10.4 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE) Automatic Protection Switch Control The Automatic Protection Switch (APS) control block filters and captures the receive automatic protection switch channel bytes (K1 and K2) allowing them to be read via the RASE APS K1 Register and the RASE APS K2 Register. The bytes are filtered for three frames before being written to these registers. A protection switching byte failure alarm is declared when twelve successive frames have been received, where no three consecutive frames contain identical K1 bytes. The protection switching byte failure alarm is removed upon detection of three consecutive frames containing identical K1 bytes. The detection of invalid APS codes is done in software by polling the RASE APS K1 Register and the RASE APS K2 Register. Bit Error Rate Monitor The Bit Error Monitor Block (BERM) calculates the received line BIP-96 error detection code (B2) based on the line overhead and synchronous payload envelope of the receive data stream. The line BIP-96 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP code is compared with the BIP-96 code extracted from the B2 bytes of the following frame. Any differences indicate that a line layer bit error has occurred. Up to 768,000 (96 BIP/frame x 8000 frames/second) bit errors can be detected per second for STS-12c/STM-4-4c rate. The BERM accumulates these line layer bit errors in a 20 bit saturating counter that can be read via the microprocessor interface. During a read, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note, this counter should be polled at least once per second to avoid saturation that in turn may result in missed bit error events. The BERM block is able to simultaneously monitor for signal fail (SF) or signal degrade (SD) threshold crossing and provide alarms through software interrupts. The bit error rates associated with the SF or SD alarms are programmable over a range of 10-3 to 10-9. Details are provided in the Operation section. Synchronization Status Extraction The Synchronization Status Extraction (SSE) Block extracts the synchronization status (S1) byte from the line overhead. The SSE block can be configured to capture the S1 nibble after three or after eight frames with the same value (filtering turned on) or after any change in the value (filtering turned off). The S1 nibble can be read via the CBI interface.
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10.5 Receive Path Overhead Processor (RPOP) The Receive Path Overhead Processor (RPOP) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope, and path level alarm indication and performance monitoring. Pointer Interpreter The Pointer Interpreter interprets the incoming pointer (H1, H2) as specified in the references. The pointer value is used to determine the location of the path overhead (the J1 byte) in the incoming STS-12c/STM-4-4c stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm three states are defined as shown below: NORM_state (NORM) AIS_state (AIS) LOP_state (LOP) The transition between states will be consecutive events (indications), e.g., three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is chosen such that the behavior is stable and insensitive to low BER. The only transition on a single event is the one from the AIS_state to the NORM_state after receiving a NDF enabled with a valid pointer value. It should be noted that, since the algorithm only contains transitions based on consecutive indications, this implies that, for example, non-consecutively received invalid indications do not activate the transitions to the LOP_state.
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Figure 6: Pointer Interpretation State Diagram
3 x eq_new_point inc_ind / dec_ind NDF_enable
NORM
3x eq_new_point
8x inv_point
8x NDF_enable
3x eq_new_point
3x AIS_ind NDF_enable
3 x AIS_ind
LOP
8 x inv_point
AIS
The following table defines the events (indications) shown in the state diagram. Table 1: Pointer Interpreter Event (Indications) Description Event (Indication) Description norm_point NDF_enable disabled NDF + ss + offset value equal to active offset enabled NDF + ss + offset value in range of 0 to 782 or enabled NDF + ss, if NDFPOR bit is set (Note that the current pointer is not updated by an enabled NDF if the pointer is out of range). H1 = 'hFF, H2 = 'hFF disabled NDF + ss + majority of I bits inverted + no majority of D bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago disabled NDF + ss + majority of D bits inverted + no majority of I bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago
AIS_ind inc_ind
dec_ind
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inv_point
not any of above (i.e., not norm_point, and not NDF_enable, and not AIS_ind, and not inc_ind and not dec_ind) disabled_NDF + ss + offset value in range of 0 to 782 but not equal to active offset majority of I bits inverted + no majority of D bits inverted majority of D bits inverted + no majority of I bits inverted active offset is defined as the accepted current phase of the SPE (VC) in the NORM_state and is undefined in the other states. enabled NDF is defined as the following bit patterns: 1001, 0001, 1101, 1011, 1000. disabled NDF is defined as the following bit patterns: 0110, 1110, 0010, 0100, 0111. the remaining six NDF codes (0000, 0011, 0101, 1010, 1100, 1111) result in an inv_ndf indication. ss bits are unspecified in SONET and has bit pattern 10 in SDH the use of ss bits in definition of indications may be optionally disabled. the requirement that previous NDF_enable, inc_ind or dec_ind be more than 3 frames ago may be optionally disabled. new_point is also an inv_point. LOP is not declared if all the following conditions exist: * the received pointer is out of range (>782), * the received pointer is static, * the received pointer can be interpreted, according to majority voting on the I and D bits, as a positive or negative justification indication, * after making the requested justification, the received pointer continues to be interpretable as a pointer justification. When the received pointer returns to an in-range value, the S/UNI622-POS will interpret it correctly.
new_point inc_req dec_req Note 1Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9 -
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Note 10 -
LOP will exit at the third frame of a three frame sequence consisting of one frame with NDF enabled followed by two frames with NDF disabled, if all three pointers have the same legal value.
The transitions indicated in the state diagram are defined in the following table. Table 2: Pointer Interpreter Transition Description Transition inc_ind/dec_ind 3 x eq_new_point NDF_enable 3 x AIS_ind 8 x inv_point 8 x NDF_enable Note 1 Note 2 Note 3 Note 4 Description offset adjustment (increment or decrement indication) three consecutive equal new_point indications single NDF_enable indication three consecutive AIS indications eight consecutive inv_point indications eight consecutive NDF_enable indications
the transitions from NORM_state to NORM_state do not represent state changes but imply offset changes. 3 x new_point takes precedence over other events and if the IINVCNT bit is set resets the inv_point count. all three offset values received in 3 x eq_new_point must be identical. "consecutive event counters" are reset to zero on a change of state except for consecutive NDF count.
The Pointer Interpreter detects loss of pointer (LOP) in the incoming STS12c/STM-4-4c stream. LOP is declared on entry to the LOP_state as a result of eight consecutive invalid pointers or eight consecutive NDF enabled indications. The alarm condition is reported in the receive alarm port and is optionally returned to the source node by signaling the corresponding Transmit Path Overhead Processor in the local S/UNI-622-POS to insert a path RDI indication. The Pointer Interpreter detects path AIS in the incoming STS-12c/STM-4-4c stream. PAIS is declared on entry to the AIS_state after three consecutive AIS indications. The alarm condition reported in the receive alarm port and is optionally returned to the source node by signaling the corresponding Transmit Path Overhead Processor in the local SONET/SDH equipment to insert a path RDI indication.
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Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications (new_point), discontinuous change of pointer alignment, and illegal pointer changes are also detected and reported by the Pointer Interpreter block via register bits. An invalid NDF code is any NDF code that does not match the NDF enabled or NDF disabled definitions. The third occurrence of equal new_point indications (3 x eq_new_point) is reported as a discontinuous change of pointer alignment event (DISCOPA) instead of a new pointer event and the active offset is updated with the receive pointer value. An illegal pointer change is defined as a inc_ind or dec_ind indication that occurs within three frames of the previous inc_ind, dec_ind or NDF_enable indications. Illegal pointer changes may be optionally disabled via register bits. The active offset value is used to extract the path overhead from the incoming stream and can be read from an internal register. SPE Timing The SPE Timing Block provides SPE timing information to the Error Monitor and the Extract blocks. The block contains a free running timeslot counter that is initialized by a J1 byte identifier (which identifies the first byte of the SPE). Control signals are provided to the Error Monitor and the Extract blocks to identify the Path Overhead bytes and to downstream circuitry to extract the ATM cell or POS payload. Error Monitor The Error Monitor Block contains two 16-bit counters that are used to accumulate path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two counters may be transferred to holding registers, and the counters reset under microprocessor control. Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted from the current frame, to the path BIP-8 computed for the previous frame. FEBEs are detected by extracting the 4-bit FEBE field from the path status byte (G1). The legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. Any other value is interpreted as zero errors. Path RDI alarm is detected by extracting bit 5 of the path status byte. The PRDI signal is set high when bit 5 is set high for five/ten consecutive frames. PRDI is set low when bit 5 is low for five/ten consecutive frames. Auxiliary RDI alarm is detected by extracting bit 6 of the path status byte. The Auxiliary RDI alarm is indicated when bit 6 is set high for five/ten consecutive frames. The Auxiliary RDI alarm is removed when bit 6 is low for five/ten consecutive frames. The
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Enhanced RDI alarm is detected when the enhanced RDI code in bits 5,6,7 of the path status byte indicates the same error codepoint for five/ten consecutive frames. The Enhanced RDI alarm is removed when the enhanced RDI code in bits 5,6,7 of the path status byte indicates the same non error codepoint for five/ten consecutive frames. The ERDII maskable interrupt is set high when bits 5, 6 & 7 of the path status byte (G1) byte are set to a new codepoint for five or ten consecutive frames. The ERDIV[2:0] signal reflects the state of the filtered ERDI value (G1 byte bits 5, 6, & 7). 10.6 Receive ATM Cell Processor (RXCP) The Receive ATM Cell Processor (RXCP) performs ATM cell delineation, provides cell filtering based on idle/unassigned cell detection and HCS error detection, and performs ATM cell payload descrambling. The RXCP also provides a four-cell deep receive FIFO. This FIFO is used to separate the STS12c/STM-4-4c line timing from the higher layer ATM system timing. Cell Delineation Cell Delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the cell header. The HCS is a CRC8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. Cells are assumed to be byte-aligned to the synchronous payload envelope. The cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location. While searching for the cell boundary location, the cell delineation circuit is in the HUNT state. When a correct HCS is found, the cell delineation state machine locks on the particular cell boundary, corresponding to the correct HCS, and enters the PRESYNC state. The PRESYNC state validates the cell boundary location. If the cell boundary is invalid, an incorrect HCS will be received within the next DELTA cells, at which time a transition back to the HUNT state is executed. If no HCS errors are detected in this PRESYNC period, the SYNC state is entered. While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in Figure 5.
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Figure 7: Cell Delineation State Diagram
correct HCS (byte by byte)
HUNT
Incorrect HCS (cell by cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell by cell)
SYNC
DELTA consecutive correct HCS's (cell by cell)
The values of ALPHA and DELTA determine the robustness of the delineation process. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6. These values result in an average time to delineation of 8 s for the STS12c/STM-4-4c rate. Descrambler The self-synchronous descrambler operates on the 48 byte cell payload only. The circuitry descrambles the information field using the x43 + 1 polynomial. The descrambler is disabled for the duration of the header and HCS fields and may optionally be disabled for the payload. Cell Filter and HCS Verification Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern. Cell filtering is optional and is enabled through the RXCP registers. Cells are passed to the receive FIFO while the cell delineation state machine is in the SYNC state as described above. When both filtering and HCS checking are enabled, cells are dropped if uncorrectable HCS errors are detected, or if the
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corrected header contents match the pattern contained in the RXCP Match Header Pattern and RXCP Match Header Mask registers. Idle or unassigned cell filtering is accomplished by writing the appropriate cell header pattern into the RXCP Match Header Pattern and RXCP Match Header Mask registers. Idle/Unassigned cells are assumed to contain the all zeros pattern in the VCI and VPI fields. The RXCP Match Header Pattern and RXCP Match Header Mask registers allow filtering control over the contents of the GFC, PTI, and CLP fields of the header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RXCP block verifies the received HCS using the polynomial, x8 + x2 + x + 1. The coset polynomial, x6 + x4 + x2 + 1, is added (modulo 2) to the received HCS octet before comparison with the calculated result. While the cell delineation state machine in Figure 7 is in the SYNC state, the HCS verification circuit implements the state machine shown in Figure 8. In normal operation, the HCS verification state machine remains in the 'Correction Mode' state. Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the state machine transitions to the 'Detection Mode' state. In this state, programmable HCS error filtering is provided. The detection of any HCS error causes the corresponding cell to be dropped. The state machine transitions back to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received with correct HCSs. The Mth cell is not discarded.
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Figure 8: HCS Verification State Diagram
ATM DELINEATION SYNC STATE
ALPHA consecutive incorrect HCS's (To HUNT state)
Apparent Multi-Bit Error (Drop Cell) No Errors Detected (Pass Cell) CORRECTION MODE
Single-Bit Error (Correct Error and Pass Cell)
Errors Detected (Drop Cell)
DETECTION MODE
DELTA consecutive correct HCS's (From PRESYNC state)
No Errors Detected In M Cells (Pass Mth Cell) No Errors Detected (Pass Cell)
Performance Monitor The Performance Monitor consists of two 8-bit saturating HCS error event counters and a 24-bit saturating receive cell counter. The first error counter accumulates correctable HCS errors, which are HCS single-bit errors, detected and corrected while the HCS Verification state machine is in the 'Correction Mode' state. The second error counter accumulates uncorrectable HCS errors, which are HCS bit errors detected while the HCS Verification state machine is in the 'Detection Mode' state or HCS bit errors detected but not corrected while the state machine is in the 'Correction Mode' state. The 24-bit receive cell counter counts all cells written into the receive FIFO. Filtered cells are not counted. Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that the counter be polled at least once per second so as not to miss any counted events.
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Receive FIFO The Receive FIFO block contains storage for 4 cells, along with management circuitry for reading and writing the FIFO. The receive FIFO provides for the separation of the physical layer timing from the system timing. Receive FIFO management functions include filling the receive FIFO, indicating when cells are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun conditions. Upon detection of an overrun, the FIFO discards the current cell and discards the incoming cells until there is room in the FIFO. FIFO overruns are indicated through a maskable interrupt and register bit and are considered a system error. 10.7 Receive POS Frame Processor (RXFP) The Receive POS Frame Processor (RXFP) performs packet extraction, provides FCS error correction, performs packet payload descrambling, and provides performance monitoring functions. The RXFP also provides a 256 byte deep receive FIFO. This FIFO is used to separate the STS-12c/STM-4-4c line timing from the link layer system timing and to handle timing differences caused by the removal of escape characters. Overhead Removal The overhead removal consists of stripping SONET/SDH overhead bytes from the data stream. Once overhead bytes are removed, the data stream consists of POS frame octets that can be fed directly to the descrambler or the POS Frame Delineation block. Descrambler When enabled, the self-synchronous descrambler operates on the POS Frame data, descrambling the data with the polynomial x43 + 1. Descrambling is performed on the raw data stream, before any POS frame delineation or byte destuffing is performed. Data scrambling can provide for a more robust system, preventing the injection of hostile patterns into the data stream. POS Frame Delineation This block accepts data one byte at a time and arranges it as POS framed octets. Frame boundaries are found by searching for the Flag Character (0x7E). Flags are also used to fill inter-packet spacing. This block removes the Flag Sequence and passes the data onto the Byte Destuffing block.
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The POS Frame Delineation is performed on the descrambled data and consists of arranging the POS framed octets. Frame boundaries are found by searching for the Flag Character (0x7E). Flags are also used to fill inter-packet spacing. This block removes the Flag Sequence and passes the data onto the Byte Destuffing block. The POS Frame format is shown on Figure 9. Figure 9: Packet Over SONET/SDH Frame Format
Flag Packet (PPP or other) FCS Flag Flag
POS Frame
In the event of a FIFO overflow caused by the FIFO being full while a packet is being received, the packet is marked with an error so it can be discarded by the system. Subsequent bytes associated with this now aborted frame are discarded. Reception of POS data resumes when a Start of Packet is encountered and the FIFO level is below the programmable Reception Initialization Level (RIL[7:0]). Byte Destuffing The byte destuffing algorithm searches the Control Escape character (0x7D). These characters, listed in Table 3, are added for transparency in the transmit direction and must be removed to recover the user data. When the Control Escape character is encountered, it is removed and the following data byte is XORed with 0x20. Therefore, any escaped data byte will be processed properly by the S/UNI-622-POS. Table 3: HDLC Byte Sequences Data Value
0x7E (Flag Sequence) 0x7D (Control Escape) HDLC Aborted Packet
Sequence 0x7D 0x5E
0x7D 0x5D 0x7D 0x7E
FCS Check The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole POS frame, after byte destuffing and data descrambling scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRC-CCITT is two bytes in size and has a generating polynomial g(x) = 1 + x5 +
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x12 + x16. The CRC-32 is four bytes in size and has a generating polynomial g(x) = 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32. The first FCS bit transmitted is the coefficient of the highest term. Packets with FCS errors are marked as such and should be discarded by the system. Figure 10: CRC Decoder
g1
g2
gn-1
Message
+
D0
+
D1
+ ...
+
Dn-1
Performance Monitor The Performance Monitor consists of four 16-bit saturating error event counters and one 24-bit saturating received good packet counter. One of the error event counters accumulates FCS errors. The second error event counter accumulates minimum length violation packets. The third error event counter accumulates maximum length violation packets. The fourth error event counter accumulates aborted packets. The 24-bit receive good packet counter counts all error free packets. Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, whichever is appropriate, so that a new period of accumulation can begin without loss of any events. The counters should be polled at least once per second so error events will not be missed. The RXFP monitors the packets for both minimum and maximum length errors. When a packet size is smaller than MINPL[7:0], the packet is marked with an error but still written into the FIFO. Malformed packets, that is packets that do not at least contain the FCS field plus one byte, are treated differently. If a malformed packet is received and FCS stripping is enabled, the packet is discarded, not written in the FIFO, and counted as a minimum packet size violation. If a malformed packet is received and FCS stripping is disabled, it is written into the FIFO since in this case the misformed packet criteria is reduced to one byte, but will still count as a minimum packet size violation. When the
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packet size exceeds MAXPL[15:0] the packet is marked with an error and the bytes beyond the maximum count are discarded. Receive FIFO The Receive FIFO block contains storage for 256 octets, along with management circuitry for reading and writing the FIFO. The receive FIFO provides for the separation of the physical layer timing from the system timing. Receive FIFO management functions include filling the receive FIFO, indicating when packets or bytes are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun conditions. Upon detection of an overrun, the FIFO aborts the current packet and discards the current incoming bytes until there is room in the FIFO. Once enough room is available, as defined by the RIL[7:0] register, the RXFP will wait for the next start of packet before writing any data into the FIFO. FIFO overruns are indicated through a maskable interrupt and register bit, and are considered a system error. 10.8 Transmit Line Interface (CSPI-622) The Transmit Line Interface allows to directly interface the S/UNI-622-POS with optical modules (ODLs) or other medium interfaces. This block performs clock synthesis and performs parallel to serial conversion on the incoming outgoing 622.08 Mbit/s data stream. Clock Synthesis The transmit clock is synthesized from a 77.76 MHz reference by the clock synthesis unit (CSU). The transfer function yields a typical low pass corner of 1 MHz, above which reference jitter is attenuated at least 20 dB per octave. The design of the loop filter and PLL is optimized for minimum intrinsic jitter. With a jitter free 77.76 MHz reference, the intrinsic jitter is typically less than 0.07 UI RMS when measured using a high pass filter with a 12 kHz cutoff frequency. The REFCLK reference should be within 20 ppm to meet the SONET/SDH freerun accuracy requirements specified in GR-253-CORE. The CSU may require a software reset when the supply voltage drops below the minimum operating level. See the CSPI-622 register description for more information. Parallel to Serial Converter The Parallel to Serial Converter (PISO) converts the transmit byte serial stream to a bit serial stream. The transmit bit serial stream appears on the TXD+/-
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PECL output. When the parallel transmit interface mode is used, the PISO block is not used. 10.9 Transmit Section Overhead Processor (TSOP) The Transmit Section Overhead Processor (TSOP) provides frame pattern insertion (A1, A2), scrambling, section level alarm signal insertion, and section BIP-8 (B1) insertion. In addition, it inserts the section data communication channel provided serially on input TSD. Line AIS Insert Line AIS insertion results in all bits of the SONET/SDH frame being set to 1 before scrambling except for the section overhead. The Line AIS Insert Block substitutes all ones as described when enabled by the TLAIS input or through an internal register accessed through the microprocessor interface. Activation or deactivation of line AIS insertion is synchronized to frame boundaries. Data Link Insert The Data Link Insert Block inserts the section data communication channel (bytes D1, D2, and D3) into the STS-12c/STM-4-4c stream when enabled by an internal register accessed via the common bus interface. The bytes to be inserted are serially input on signal TSLD at a nominal 192 kbit/s rate. Timing for upstream processing of the data communication channel is provided by the TSDCLK signal that is output by the Data Link Insert Block. TSDCLK is derived from a 216 kHz clock that is gapped to yield an average frequency of 192 kHz. TSD is sampled with timing aligned to TSDCLK. BIP-8 Insert The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1) into the transmit stream. The BIP-8 calculation is based on the scrambled data of the complete STS12c/STM-4-4c frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 code is then inserted into the B1 byte of the following frame before scrambling. BIP-8 errors may be continuously inserted under register control for diagnostic purposes.
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Framing and Identity Insert The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and trace/growth bytes (J0/Z0) into the STS-12c/STM-4-4c frame. Framing bit errors may be continuously inserted under register control for diagnostic purposes. Scrambler The Scrambler Block utilizes a frame synchronous scrambler to process the transmit stream when enabled through an internal register accessed via the microprocessor interface. The generating polynomial is x7 + x6 + 1. Precise details of the scrambling operation are provided in the references. Note that the framing bytes and the identity bytes are not scrambled. All zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes. The POUT[7:0] outputs are provided by the Scrambler block and are updated with timing aligned to TCLK. It also provides the FPOUT signal. 10.10 Transmit Line Overhead Processor (TLOP) The Transmit Line Overhead Processor (TLOP) provides line level alarm signal insertion, and line BIP-96 insertion (B2). In addition, it inserts the line data communication provided serially on input TLD. APS Insert The APS Insert Block inserts the two automatic protection switch (APS) channel bytes in the Line Overhead (K1 and K2) into the transmit stream when enabled by an internal register. Data Link Insert The Data Link Insert Block inserts the line data communication channel (DCC) (bytes D4 to D12) into the STS-12c/STM-4-4c stream when enabled by an internal register. The D4 to D12 bytes are input serially using the TLD signal at a nominal 576 kbit/s rate. Timing for processing of the line DCC is provided by the TLDCLK output. TLDCLK is derived from a 2.16 MHz clock that is gapped to yield an average frequency of 576 kHz. Line BIP Calculate The Line BIP Calculate Block calculates the line BIP-96 error detection code (B2) based on the line overhead and synchronous payload envelope of the transmit
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stream. The line BIP-96 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-96 code is inserted into the B2 byte positions of the following frame. BIP-96 errors may be continuously inserted under register control for diagnostic purposes. Line RDI Insert The Line RDI Insert Block controls the insertion of line remote defect indication. Line RDI insertion is enabled through register control. Line RDI is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the K2 byte contained in the transmit stream. Line FEBE Insert The Line FEBE Insert Block accumulates line BIP-96 errors (B2) detected by the Receive Line Overhead Processor and encodes far end block error indications in the transmit Z2 byte. 10.11 Transmit Path Overhead Processor (TPOP) The Transmit Path Overhead Processor (TPOP) provides transport frame alignment generation, pointer generation (H1, H2), path overhead insertion and the insertion of path level alarm signals. Pointer Generator The Pointer Generator Block generates the outgoing payload pointer (H1, H2) as specified in the references. The concatenation indication (the NDF field set to 1001, I-bits and D-bits set to all ones, and unused bits set to all zeros) is inserted in the second and third pointer byte locations in the transmit stream. (1) A "normal pointer value" locates the start of the SPE. Note: 0 "normal pointer value" 782, and the new data flag (NDF) field is set to 0110. Note that values greater than 782 may be inserted, using internal registers, to generate a loss of pointer alarm in downstream circuitry. (2) Arbitrary "pointer values" may be generated using internal registers. These new values may optionally be accompanied by a programmable new data flag. New data flags may also be generated independently using internal registers. (3) Positive pointer movements may be generated using a bit in an internal register. A positive pointer movement is generated by inverting the five I-bits of the pointer word. The SPE is not inserted during the positive stuff opportunity
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byte position, and the pointer value is incremented by one. Positive pointer movements may be inserted once per frame for diagnostic purposes. (4) Negative pointer movements may be generated using a bit in an internal register. A negative pointer movement is generated by inverting the five D-bits of the pointer word. The SPE is inserted during the negative stuff opportunity byte position, the H3 byte, and the pointer value is decremented by one. Negative pointer movements may be inserted once per frame for diagnostic purposes. The pointer value is used to insert the path overhead into the transmit stream. The current pointer value may be read via internal registers. BIP-8 Calculate The BIP-8 Calculate Block performs a path bit interleaved parity calculation on the SPE of the transmit stream. Details are provided in the references. The resulting parity byte is inserted in the path BIP-8 (B3) byte position of the subsequent frame. BIP-8 errors may be continuously inserted under register control for diagnostic purposes. FEBE Calculate The FEBE Calculate Block accumulates far end block errors on a per frame basis, and inserts the accumulated value (up to maximum value of eight) in the FEBE bit positions of the path status (G1) byte. The FEBE information is derived from path BIP-8 errors detected by the receive path overhead processor, RPOP. Far end block errors may be inserted under register control for diagnostic purposes. 10.12 Transmit ATM Cell Processor (TXCP) The Transmit ATM Cell Processor (TXCP) provides rate adaptation via idle/unassigned cell insertion, provides HCS generation and insertion, and performs ATM cell scrambling. The TXCP contains a four cell transmit FIFO. An idle or unassigned cell is transmitted if a complete ATM cell has not been written into the FIFO. Transmit FIFO The Transmit FIFO is responsible for holding cell provided through the Transmit System Interface until they are transmitted. The transmit FIFO can accommodate a maximum of 4 cells. The cells are written in with a single 16 bit data bus running off TFCLK and are read out using the SONET/SDH clock. Internal read and write pointers track the cells and indicate the fill status of the
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Transmit FIFO. Separate read and write clock domains provide for separation of the physical layer line timing from the System Link layer timing (TFCLK). Idle/Unassigned Cell Generator The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell stream when enabled. Registers are provided to program the GFC, PTI, and CLP fields of the idle cell header and the idle cell payload. The idle cell HCS is automatically calculated and inserted. Scrambler The Scrambler scrambles the 48 octet information field. Scrambling is performed using a parallel implementation of the self-synchronous scrambler (x43 + 1 polynomial). The cell headers are transmitted unscrambled, and the scrambler may optionally be disabled. HCS Generator The HCS Generator performs a CRC-8 calculation over the first four header octets. A parallel implementation of the polynomial, x8+x2+x+1, is used. The coset polynomial, x6+x4+x2+1, is added (modulo 2) to the residue. The HCS Generator optionally inserts the result into the fifth octet of the header. 10.13 Transmit POS Frame Processor (TXFP) The Transmit POS Frame Processor (TXFP) provides rate adaptation by transmitting flag sequences (0x7E) between packets, provides FCS generation and insertion, performs packet data scrambling, and provides performance monitoring functions. The TXFP contains a 256 byte transmit FIFO. This FIFO is used to separate the STS-12c/STM-4-4c line timing from the link layer system timing and to handle timing differences caused by insertion of escape characters. Transmit FIFO The Transmit FIFO is responsible for holding packets provided through the Input Interface until they are transmitted. The transmit FIFO can accommodate a maximum of 256 bytes. There is no limit on the number of packets that can be stored. Octets are written in with a single 16 bit data bus running off TFCLK and are read out with a single 8-bit data bus running off the SONET/SDH clock. Separate read and write clock domains provide for separation of the physical layer line timing from the system link layer timing (TFCLK).
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Internal read and write pointers track the insertion and removal of octets, and indicate the fill status of the Transmit FIFO. These status indications are used to detect underrun and overrun conditions, abort packets as appropriate on both system and line sides, control flag insertion and to generate the TPA outputs. The TXFP does not abort packets under an FIFO overrun condition. The corrupted packet will be send with properly calculated FCS if the FCS feature is enabled. Since overruns can be avoided by setting the FIFO high and low watermarks, this limitation should not affect system performance. POS Frame Generator The POS Frame Generator runs off of the SONET/SDH sequencer to create the POS frames to be transmitted, whose format is shown in Figure 9. Flags are inserted whenever the Transmit FIFO is empty and there is no data to transmit. When there is enough data to be transmitted, the block operates normally; it removes packets from the Transmit FIFO and transmits them. In addition, FCS generation, error insertion, byte stuffing, and scrambling can be optionally enabled. Figure 11: Packet Over SONET/SDH Frame Format
Flag Packet (PPP or other) FCS Flag Flag
POS Frame
In the event of a FIFO underflow caused by the FIFO being empty while a packet is being transmitted, the packet is aborted by transmitting the Abort Sequence. The Abort Sequence consists of an Escape Control character (0x7D) followed by the Flag Sequence (0x7E). Bytes associated with this aborted frame are still read from the FIFO but are discarded and replaced with the Flag Sequence in the outgoing data stream. Transmission of data resumes a start of the next packet is encountered in the FIFO data stream. The POS Frame Generator also performs inter-packet gaping. This operation consists of inserting a programmable number of Flag Sequence characters between each POS frame transmission. This feature allows to control the system effective data transmission rate if required. For correct operation, the TXFP only supports packets ranging in size from 2 bytes to 65534 bytes in length.
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FCS Generator The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole POS frame, before byte stuffing and data scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRCCCITT is two bytes in size and has a generating polynomial g(x) = 1 + x5 + x12 + x16. The CRC-32 is four bytes in size and has a generating polynomial g(x) = 1 + x + x2 + x4 + x5 + x7 + x8 + x10 + x11 + x12 + x16 + x22 + x23 + x26 + x32. The first FCS bit transmitted is the coefficient of the highest term. When transmitting a packet from the Transmit FIFO, the FCS Generator appends the result after the last data byte, before the closing flag. Note that the Frame Check Sequence is the one's complement of the CRC register after calculation ends. FCS calculation and insertion can be disabled. Figure 12: CRC Generator
g1
g2
gn-1
D0
+
LSB
D1
+ ...
+
Dn-1
+
Message
Parity Check Digits
MSB
An error insertion mechanism is provided for system diagnosis purposes. Error insertion is performed by inverting the resulting FCS value, before transmission. This should cause an FCS Error at the far end. Byte Stuffing The POS Frame generator provides transparency by performing byte stuffing. This operation is done after the FCS calculation. Two characters are being escaped, the Flag Sequence (0x7E) and the Escape Character itself (0x7D). When a character is being escaped, it is XORed with 0x20 before transmission and preceded by the Control Escape (0x7D) character.
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Table 4: HDLC Byte Sequences Data Value 0x7E (Flag Sequence) 0x7D (Control Escape) HDLC Abort Sequence Data Scrambling The Scrambler will optionally scramble the whole packet data, including the FCS and the flags. Scrambling is performed after the POS frame is formed using a parallel implementation of the self-synchronous scrambler polynomial, x43+1. On reset, the scrambler is set to all ones to ensure scrambling on start-up. The scrambler may optionally be completely disabled. Data scrambling can provide for a more robust system preventing the injection of hostile patterns into the data stream. SONET/SDH Framer The SONET/SDH Framer gaps the POS frames in order to insert the SONET/SDH framing and overhead bytes (Section/Line Overhead and Path Overhead). The framer uses framing alignment information provided by the TPOP TSB to perform its function. The TXFP does not set any SONET/SDH overhead bytes. 10.14 SONET/SDH Path Trace Buffer (SPTB) The SONET/SDH Section Trace Buffer (SPTB) block can handle both 64-byte CLLI messages in SONET and 16-byte E.164 messages in SDH. This block operates similarly to the SONET/SDH Section Trace Buffer (SSTB). Receive Trace Message Receiver The Trace Message Receiver (TMR) processes the receive trace message, and consists of three sub-processes: Framer, Persistency, and Compare. The Framer handles the incoming 16-byte message by synchronizing to the byte with the most significant bit set high, and places that byte in the first location in the capture page of the internal RAM. In the case of the 64-byte message, the Framer synchronizes to the trailing carriage return (0x0D), line feed (0x0A) sequence and places the next byte in the first location in the capture page of the internal RAM. The Framer block maintains an internal representation of the resulting 16-byte or 64-byte "frame" cycle. If the phase of the start of frame Sequence 0x7D 0x5E 0x7D 0x5D 0x7D 0x7E
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shifts, the framer adjusts accordingly and resets the persistency counter and increments the unstable counter. Frame synchronization may be disabled, in which case the RAM acts as a circular buffer. The Persistency process checks for repeated reception of the same 16-byte or 64-byte trace message. An unstable counter is incremented for each message that differs from the previous received message. For example, a single corrupted message in a field of constant messages causes the unstable count to increment twice, once on receipt of the corrupted message, and again on the next (uncorrupted) message. A section/path trace message unstable alarm is declared when the count reaches eight. The persistency counter is reset to zero, the unstable alarm is removed, and the trace message is accepted when the same 16-byte or 64-byte message is received three or five times consecutively (as determined by an internal register bit). The accepted message is passed to the Compare process for comparison with the expected message. A receive trace message mismatch alarm is declared if the accepted message (i.e. the message that passed the persistency check) does not match the expected message (previously downloaded to the receive expected page by the microprocessor). The mismatch alarm is removed if the accepted message is allzero, or if the accepted message is identical to the expected message. Overhead Byte Receiver The Overhead Byte Receiver (OBR) processes the path signal label byte (C2)The OBR consists of two sub-processes: Persistency and Compare. The Persistency process checks for the repeated reception of the same C2 byte. An unstable counter is incremented for each received C2 byte that differs from the byte received in the previous frame. For example, a single corrupted byte value in a sequence of constant values causes the unstable count to increment twice, once on receipt of the corrupted value, and again on the next (uncorrupted) value. A path signal label unstable alarm or a synchronization status unstable alarm is declared when either unstable counter reaches five. The unstable counter is reset to zero, the unstable alarm is removed, and the byte value is accepted when the same label is received in five consecutive frames. The accepted value is passed to the Compare process for comparison with the expected value. A path signal label mismatch alarm or a synchronization status mismatch alarm is declared if the accepted C2 byte (i.e. the byte value that has passed the
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persistency check) does not match the expected C2 byte (previously downloaded by the microprocessor). The OBR mismatch mechanism follows the table below: Table 5: OBR Mismatch Mechanism Expect 00 00 00 01 01 01 XX XX XX XX Receive 00 01 XX 00 01 XX 00 01 XX YY Action Match Mismatch Mismatch Mismatch Match Match Mismatch Match Match Mismatch
Note: XX, YY are equal to anything except 00H or 01H and are not equal to each other. Transmit Trace Buffer The Trace Transmit Buffer (TTB) sources the 16-byte or 64-byte trace identifier message. The TTB contains one page of transmit trace identifier message memory. Identifier message data bytes are written by the microprocessor into the message buffer and inserted in the transmit stream. When the microprocessor is updating the transmit page buffer, the TTB may be programmed to transmit null characters to prevent transmission of partial messages. 10.15 SONET/SDH Section Trace Buffer (SSTB) The SONET/SDH Section Trace Buffer (SSTB) block can handle both 64-byte CLLI messages in SONET and 16-byte E.164 messages in SDH. This block operates similarly to the SONET/SDH Path Trace Buffer (SPTB) except the C2 byte is also processed.
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Receive Trace Message Receiver The Trace Message Receiver (TMR) processes the receive trace message, and consists of three sub-processes: Framer, Persistency, and Compare. The Framer handles the incoming 16-byte message by synchronizing to the byte with the most significant bit set high, and places that byte in the first location in the capture page of the internal RAM. In the case of the 64-byte message, the Framer synchronizes to the trailing carriage return (0x0D), line feed (0x0A) sequence and places the next byte in the first location in the capture page of the internal RAM. The Framer block maintains an internal representation of the resulting 16-byte or 64-byte "frame" cycle. If the phase of the start of frame shifts, the framer adjusts accordingly and resets the persistency counter and increments the unstable counter. Frame synchronization may be disabled, in which case the RAM acts as a circular buffer. The Persistency process checks for repeated reception of the same 16-byte or 64-byte trace message. An unstable counter is incremented for each message that differs from the previous received message. For example, a single corrupted message in a field of constant messages causes the unstable count to increment twice, once on receipt of the corrupted message, and again on the next (uncorrupted) message. A section/path trace message unstable alarm is declared when the count reaches eight. The persistency counter is reset to zero, the unstable alarm is removed, and the trace message is accepted when the same 16-byte or 64-byte message is received three or five times consecutively (as determined by an internal register bit). The accepted message is passed to the Compare process for comparison with the expected message. A receive trace message mismatch alarm is declared if the accepted message (i.e. the message that passed the persistency check) does not match the expected message (previously downloaded to the receive expected page by the microprocessor). The mismatch alarm is removed if the accepted message is allzero, or if the accepted message is identical to the expected message. Transmit Trace Buffer (TTB) The TTB sources the 16-byte or 64-byte trace identifier message. The TTB contains one page of transmit trace identifier message memory. Identifier message data bytes are written by the microprocessor into the message buffer and inserted in the transmit stream. When the microprocessor is updating the transmit page buffer, the TTB may be programmed to transmit null characters to prevent transmission of partial messages.
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10.16 ATM UTOPIA and Packet over SONET/SDH POS-PHY System Interfaces The S/UNI-622-POS system interface can be configured for ATM or POS mode. When configured for ATM applications, the system interface provides either a UTOPIA level 2 compliant bus or a UTOPIA Level 3 compatible bus to allow the transfer of ATM cells between the ATM layer device and the S/UNI-622-POS. When configured for POS applications, the system interface provides either a POS-PHY Level 2 or POS-PHY Level 3 compliant bus and provides a byte level transfer interface that allows the transfer of data packets between the link layer device and the S/UNI-622-POS. The link layer device can implement various protocols, including PPP. 10.16.1 Receive ATM Interface
The Receive ATM FIFO (RXCP) provides FIFO management at the S/UNI-622POS receive cell interface. The receive FIFO contains four cells. The FIFO provides the cell rate decoupling function between the transmission system physical layer and the ATM layer. In general, the management functions include filling the receive FIFO, indicating when the receive FIFO contains cells, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions. UTOPIA Level 2 Interface The UTOPIA Level 2 compliant interface accepts a read clock (RFCLK) and read enable signal (RENB). The interface indicates the start of a cell (RSOC) and the receive cell available status (RCA) when data is read from the receive FIFO (using the rising edges of RFCLK). The RCA status changes from available to unavailable when the FIFO is either empty (when RCALEVEL0 is high) or near empty (when RCALEVEL0 is low). This interface also indicates FIFO overruns via a maskable interrupt and register bits. Read accesses while RCA is a logic zero will output invalid data. The FIFO is reset on FIFO overrun, causing up to 4 cells to be lost. UTOPIA Level 3 Interface The UTOPIA Level 3 compliant interface accepts a read clock (RFCLK) and read enable signal (RENB). The interface indicates the start of a cell (RSOC) when data is read from the receive FIFO (using the rising edges of RFCLK). The RVAL signal indicates when data on the receive data bus RDAT[7:0] is valid. The RPRTY signal reports the parity on the RDAT[7:0] bus (selectable as odd or even parity). RVAL will not assert until RENB is asserted. This interface also indicates FIFO overruns via a maskable interrupt and register bits. Read accesses while
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RVAL is low are ignored and will output invalid data. The FIFO is reset on FIFO overrun, causing up to 4 cells to be lost. 10.16.2 Receive POS Interface
The Receive POS FIFO (RXFP) provides FIFO management at the S/UNI-622POS receive packet interface. The receive FIFO contains 256 bytes. The FIFO provides the system rate decoupling function between the transmission system physical layer and the link layer, and to handle timing differences caused by the removal of escape characters. The interface can be configured either as a 16-bit POS-PHY Level 2 compliant interface, or as an 8-bit POS-PHY Level 3 compliant interface. POS-PHY Level 2 The POS-PHY Level 2 Interface is an extension to the UTOPIA interface defined for the transfer of ATM cells. The RSOP signal is used to identify the start of a packet, the RPA signal notifies the system side that data is in the receive FIFO (when a programmable number of bytes in a single packet is received or when an end of packet is available); the RDATA[15:0] bus transfer the data from the FIFO across the system interface; the RPRTY signal determines the parity on the RDAT bus (selectable as odd or even parity); the RFCLK is used to read words from the FIFO interface; and the RENB is used to initiate reads from the receive FIFO. Signal REOP (Receive End of Packet) is used to identify the end of a packet. Signal RMOD (Receive Mod) is provided to indicate whether 1 or 2 bytes are valid on the final word transfer when in 16-bit mode (REOP is asserted). Signal RERR (Receive Error) is provided to indicate that an error in the received packet has occurred (may have several causes, including an abort sequence and an FCS error). The receive data valid signal, RVAL, plays a special role in this interface. The data signals shall be considered valid only when RVAL is asserted. RVAL is asserted when a data transfer is initiated, conditional to RPA being also asserted. Once the transfer is initiated, RVAL will remain asserted until either the FIFO is empty or an end of packet is encountered. Once deasserted, RVAL will remain low until the current PHY is deselected and another or the same PHY is reselected. RVAL allows the link layer device to align data transfers with packet boundaries, making it easier to manage packet buffers. RVAL should be used at all times when RENB is low to qualify the receive data stream due to RPA falsely indicating data in the FIFO. See the Functional Timing section for more information.
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POS-PHY Level 3 The POS-PHY Level 3 compliant interface is an extension to the POS-PHY Level 2 Interface. The interface accepts a read clock (RFCLK) and read enable signal (RENB) when data is read from the receive FIFO (using the rising edge of the RFCLK). The start of packet RSOP marks the first byte of receive packet data on the RDAT[7:0]. The RPRTY signal determine the parity on the RDAT[7:0] bus (selectable as odd or even parity). The end of a packet is indicated by the REOP signal. Signal RERR is provided to indicate that an error in the received packet has occurred (the error may have several causes include an abort sequence or an FCS error). The RVAL signal is used to indicate when RSOP, REOP, RERR and RDAT[7:0] are valid. This interface also indicates FIFO overruns via a maskable interrupt and register bits. Read accesses while RVAL is low are ignored and will output invalid data. RVAL will not assert until RENB is asserted. 10.16.3 Transmit ATM Interface
The ATM Transmit FIFO (TXCP) provides FIFO management and the S/UNI-622POS transmit cell interface. The transmit FIFO contains four cells. The FIFO depth may be programmed to four, three, two, or one cells. The FIFO provides the cell rate decoupling function between the transmission system physical layer and the ATM layer. In general, the management functions include emptying cells from the transmit FIFO, indicating when the transmit FIFO is full, maintaining the transmit FIFO read and write pointers and detecting a FIFO overrun condition. The interface can be configured either as a 16-bit UTOPIA Level 2 interface, or as an 8-bit UTOPIA Level 3 interface. UTOPIA Level 2 Interface The UTOPIA Level 2 compliant interface accepts a write clock (TFCLK), a write enable signal (TENB), the start of a cell (TSOC) indication, and the parity bit (TPRTY), when data is written to the transmit FIFO (using the rising edges of TFCLK). The interface provides the transmit cell available status (TCA) which can transition from "available" to "unavailable" when the transmit FIFO is near full (when TCALEVEL0 is low) or when the FIFO is full (when TCALEVEL0 is high) and can accept no more writes. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells by the FIFODP[1:0]
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bits of the TXCP Configuration 2 register. If the programmed depth is less than four, more than one cell may be written after TCA is asserted as the TXCP still allows four cells to be stored in its FIFO. This interface also indicates FIFO overruns via a maskable interrupt and register bit, but write accesses while TCA is low are not processed. The TXCP automatically transmits idle cells until a full cell is available to be transmitted. UTOPIA Level 3 Interface The UTOPIA Level 3 compliant interface accepts a write clock (TFCLK), a write enable signal (TENB), the start of a cell (TSOC) indication and the parity bit (TPRTY) when data is written to the transmit FIFO (using the rising edges of the TFCLK). To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells by the FIFODP[1:0] bits of the TXCP Configuration 2 register. If the programmed depth is less than four, more than one cell may be written after TCA is asserted as the TXCP still allows four cells to be stored in its FIFO. The interface also indicates FIFO overruns via a maskable interrupt and register bits. The TXCP automatically transmits idle cells until a full cell is available to be transmitted. 10.16.4 Transmit POS Interface
The Transmit POS FIFO (RXFP) provides FIFO management at the S/UNI-622POS transmit packet interface. The transmit FIFO contains 256 bytes. The FIFO provides the system rate decoupling function between the transmission system physical layer and the link layer, and to handle timing differences caused by the insertion of escape characters. POS-PHY Level 2 Interface The POS-PHY Level 2 Interface is an extension to the UTOPIA 2 interface defined for the transfer of ATM cells. POS-PHY byte-level transfer mode is supported. The TSOP signal is used to identify the start of a packet; the TPA signal notify the system side that the transmit FIFO is not full (the POS processor will not start transmitting a packet until a programmable number of bytes for a single packet or the entire packet is in the FIFO; the TDAT[15:0] bus transfer the data to the FIFO from the system interface; the TPRTY signal determines the parity on the TDAT bus (selectable as odd or even parity); the TFCLK is used to write words to the FIFO interface; and finally the TENB is used to initiate writes to the transmit
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FIFO. The TXCP automatically transmits idle flag characters until sufficient data is available in the transmit FIFO to start transmission. The TEOP signal (Transmit End of Packet) is used to identify the end of a packet. The TMOD signal (Transmit Mod) is provided to indicate whether 1 or 2 bytes are valid of the final word transfer (TEOP is asserted). TMOD is only valid in 16-bit mode of operation. The TERR signal (Transmit Error) is provided to error a packet that has begun transmission (the packet will be aborted). POS-PHY Level 3 Interface The POS-PHY Level 3 compliant interface accepts a write clock (TFCLK), a write enable signal (TENB), the start of packet (TSOP) indication, the end of packet (TEOP) indication, errored packet (TERR) indication and the parity bit (TPRTY) when data is written to the transmit FIFO (using the rising edges of the TFCLK). The TPA signal notifies that the transmit FIFO is not full (the POS processor will not start transmitting a packet until a programmable number of bytes for a single packet or the entire packet is in the FIFO). A packet may be aborted by asserting the TERR signal at the end of the packet. The interface also indicates FIFO overruns via a maskable interrupt and register bits. The TXCP automatically transmits idle flag characters until sufficient data is available in the transmit FIFO to start transmission. 10.17 WAN Synchronization Controller (WANS) The WANS provides hardware support to implement a local clock reference compliant to SONET/SDH Stratum 3 clock specifications (GR-253-CORE & GR1244-CORE) in wander transfer, long term and holdover stability. The WANS block is intended to be used in conjunction with an external processor, digital to analog converter (DAC), analog circuitry and voltage control crystal oscillator (VCXO). In general, WANS block implements the phase detector of a phase lock loop structure which relies on an external processor and a VCXO to produce the Stratum 3 clock as shown in Figure 13. The WANS performs a digital phase comparison between the recovered receive clock (receive line rate clock RCLK from the CRU-622) and the reference clock used to generate the transmit stream (REFCLK+/- supplied by the VCXO).
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Figure 13. WANS PLL Block Diagram
External VCXO
TXD+/-
CSU-622
PISO-622
TCLK SONET/SDH Transmit Stream
DAC
REFCLK+/-
WANS (Phase Detector)
Microprocessor Interface
Filtering/ Correction (Software)
RXD+/-
CRU-622
SIPO-622
RCLK SONET/SDH Recieve Stream
The software running on the external processor is responsible for performing: digital loop filtering, temperature compensation, VCXO linearity compensation; determining the validity of the timing reference; and performing reference switchover. The VCXO creates the 77.76 MHz Stratum 3 reference clock which the CSU-622 will synthesize to the desired 622.08 MHz transmit clock. Thus, the WANS PLL structure can phase lock the SONET/SDH transmit serial stream to the SONET/SDH receive serial stream. With appropriate software filtering and compensation, the device may meet SONET/SDH Stratum 3 clock specifications (GR-253-CORE & GR-1244-CORE) in wander transfer, long term and holdover stability. A description of how to program and use the WANS feature is available in the S/UNI-622-POS reference design (PMC-981070). A description of the functionality supplied by the WANS block is given below. Phase Comparison The phase comparison between the receive recovered clock (RCLK) and the transmit reference clock (REFCLK+/-) is implemented by sampling, at a fixed interval specified by the Reference Counter, the output of the Phase Counter. The Reference Counter is clocked by RCLK while the Phase Counter is clocked by the REFCLK+/- clock. Successive reading of the value obtained, referred as the phase sample (PHSAMP), can be used to calculate the phase relation between both clocks. Both the Reference Counter and the Phase Counter are programmable counters
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and are set to have equal cycle period. Therefore, if REFCLK+/- was phased locked to RCLK, successive readings of the phase sample would be equal. The phase sample value will increase or decrease depending if REFCLK+/- is faster or slower than RCLK. At each reference period, a signal enabling the sampling (SAMPLEN) of the Phase Counter is produced. This signal is resynchronized to REFCLK+/- to avoid any potential metastability problem that could result due to the asynchronous nature of both clocks. Phase Reacquisition Control The Phase Reacquisition Control circuit prevents using the phase sample from both sides of the counter wrap-around point when performing the Phase Sample averaging. The Phase Count is first divided in four quadrants, each equal to approximately a quarter of the Phase Count. Comparators are used to determine in which quadrant each phase sample is located. When two successive samples (one in the first quadrant and the other in the last quadrant) are seen, the Reference Phase Alignment Flag (RPHALFLG) is generated. Upon reception of this signal, the Phase Counter is reset to align the phase count sampling point towards its middle count. This signal is also sent to the Phase Averager circuit. The generation of this signal may be squelched by setting the AUTOREAC bit of the WANS configuration register. Phase Averager To provide some noise immunity and improve the resolution of the phase detector algorithm of the WANS, the phase samples are averaged over a programmable number of samples. Although referred to as an averaging process, it is truly an accumulation process. It retains full resolution, i.e. no division is performed on the accumulated value. The Phase Word includes an integer and a fractional part. The number of averaging samples sets the size of the fractional part. A programmable counter, the Sample Counter, is incremented at each SAMPLEN signal. This Sample Counter defines the Phase Averaging Period, equal to the Reference Period times the programmed number of phase samples. At the end of this period, the accumulated phase sample value is transferred to the Phase Word register. The Phase Word (PHAWORD) is then accessible by an external processor. A timer flag (TIMFLG) is raised at the end of each averaging period. The flag may be used to generate an interrupt request to an external processor.
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Because it indicates that the averaging process includes invalid sample values, the RPHALFLG signal also prevents the Phase Word register from being updated at the end of the current Phase Averaging period. The RPHAFLG signal indicates this event by sending the Reference Phase Alignment condition signal (RPHALGN) to the CBI status register. The RPHALGN signal is reset at the end of the following valid Phase Averaging period. 10.18 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-622-POS identification code is 0x353570CD hexadecimal. 10.19 Microprocessor Interface The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the S/UNI-622-POS. In the following section every register is documented and identified using the register number (REG #). Addresses that are not shown are not used and must be treated as Reserved. Table 6: Register Memory Map
Address 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F Register Description S/UNI-622-POS Master Reset and Identity S/UNI-622-POS Master Configuration #1 S/UNI-622-POS Master Configuration #2 S/UNI-622-POS Clock Monitors S/UNI-622-POS Master Interrupt Status #1 S/UNI-622-POS Master Interrupt Status #2 S/UNI-622-POS APS Control and Status S/UNI-622-POS Miscellaneous Configuration S/UNI-622-POS Auto Line RDI Control S/UNI-622-POS Auto Path RDI Control S/UNI-622-POS Auto Enhanced Path RDI Control S/UNI-622-POS Receive RDI and Enhanced RDI Control S/UNI-622-POS Receive Line AIS Control S/UNI-622-POS Receive Path AIS Control S/UNI-622-POS Receive Alarm Control #1 S/UNI-622-POS Receive Alarm Control #2
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Address 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F 020 021 022 023 024 025 026 027 028 029 02A 02B 02C 02D 02E 02F 030 030 031 031 032 033 033 034 035
Register Description RSOP Control/Interrupt Enable RSOP Status/Interrupt Status RSOP Section BIP-8 LSB RSOP Section BIP-8 MSB TSOP Control TSOP Diagnostic TSOP Reserved TSOP Reserved RLOP Control/Status RLOP Interrupt Enable/Interrupt Status RLOP Line BIP-96 LSB RLOP Line BIP-96 RLOP Line BIP-96 MSB RLOP Line FEBE LSB RLOP Line FEBE RLOP Line FEBE MSB TLOP Control TLOP Diagnostic TLOP Transmit K1 TLOP Transmit K2 TLOP Transmit Synchronization Message (S1) TLOP Transmit J0/Z0 Reserved Reserved SSTB Control SSTB Section Trace Identifier Status SSTB Indirect Address Register SSTB Indirect Data Register SSTB Reserved SSTB Reserved SSTB Reserved SSTB Reserved RPOP Status/Control (EXTD=0) RPOP Status/Control (EXTD=1) RPOP Interrupt Status (EXTD=0) RPOP Interrupt Status (EXTD=1) RPOP Pointer Interrupt Status RPOP Interrupt Enable (EXTD=0) RPOP Interrupt Enable (EXTD=1) RPOP Pointer Interrupt Enable RPOP Pointer LSB
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Address 036 037 038 039 03A 03B 03C 03D 03E 03F 040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E
Register Description RPOP Pointer MSB RPOP Path Signal Label RPOP Path BIP-8 LSB RPOP Path BIP-8 MSB RPOP Path FEBE LSB RPOP Path FEBE MSB RPOP RDI RPOP Ring Control RPOP Reserved RPOP Reserved TPOP Control/Diagnostic TPOP Pointer Control TPOP Reserved TPOP Current Pointer LSB TPOP Current Pointer MSB TPOP Arbitrary Pointer LSB TPOP Arbitrary Pointer MSB TPOP Path Trace TPOP Path Signal Label TPOP Path Status TPOP Reserved TPOP Reserved TPOP Reserved TPOP Reserved TPOP Concatenation LSB TPOP Concatenation MSB SPTB Control SPTB Path Trace Identifier Status SPTB Indirect Address Register SPTB Indirect Data Register SPTB Expected Path Signal Label SPTB Path Signal Label Status SPTB Reserved SPTB Reserved CSPI Configuration CSPI Status CSPI Reserved CSPI Reserved CRSI Configuration CRSI Status CRSI Reserved
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Address 05F 060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 075 076 077 078 079 07A 07B 07C 07D 07E 07F 080 081 082 083 084 085 086 087
Register Description CRSI Reserved RXCP Configuration 1 RXCP Configuration 2 RXCP FIFO/UTOPIA Control and Configuration RXCP Interrupt Enable and Counter Status RXCP Status/Interrupt Status RXCP LCD Count Threshold LSB RXCP LCD Count Threshold MSB RXCP Idle Cell Header Pattern RXCP Idle Cell Header Mask RXCP Corrected HCS Error Count RXCP Uncorrected HCS Error Count RXCP Received Cell Count LSB RXCP Received Cell Count RXCP Received Cell Count MSB RXCP Idle Cell Count LSB RXCP Idle Cell Count RXCP Idle Cell Count MSB RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved RXCP Reserved TXCP Configuration 1 TXCP Configuration 2 TXCP Transmit Cell Status TXCP Interrupt Enable/Status TXCP Idle Cell Header Control TXCP Idle Cell Payload Control TXCP Transmit Cell Counter LSB TXCP Transmit Cell Counter
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Address 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 095 096 097 098 099 09A 09B 09C 09D 09E 09F 0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1
Register Description TXCP Transmit Cell Counter MSB TXCP Reserved TXCP Reserved TXCP Reserved TXCP Reserved TXCP Reserved TXCP Reserved TXCP Reserved RUL3 Configuration RUL3 Reserved TUL3 Configuration TUL3 Reserved DLL RFCLK DLL RFCLK DLL RFCLK DLL TFCLK DLL TFCLK DLL TFCLK
DLL TFCLK
DLL PTCLK DLL PTCLK DLL PTCLK DLL PTCLK RXFP Configuration RXFP Configuration/Interrupt Enable RXFP Interrupt Status RXFP Minimum Packet Length RXFP Maximum Packet Length LSB RXFP Maximum Packet Length MSB RXFP Receive Initiation Level RXFP Receive Packet Available High Mark RXFP Receive Byte Counter LSB RXFP Receive Byte Counter RXFP Receive Byte Counter RXFP Receive Byte Counter MSB RXFP Receive Frame Counter LSB RXFP Receive Frame Counter RXFP Receive Frame Counter MSB RXFP Aborted Frame Count LSB RXFP Aborted Frame Count MSB RXFP FCS Error Frame Count LSB
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Address 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0DA
Register Description RXFP FCS Error Frame Count MSB RXFP Minimum Length Frame Count LSB RXFP Minimum Length Frame Count MSB RXFP Maximum Length Frame Count LSB RXFP Maximum Length Frame Count MSB RXFP Reserved RXFP Reserved RXFP Reserved RXFP Reserved RXFP Reserved RXFP Reserved RXFP Reserved RXFP Reserved RXFP Reserved TXFP Interrupt Enable/Status TXFP Configuration TXFP Control TXFP Transmit Packet Available Low Water Mark TXFP Transmit Packet Available High Water Mark TXFP Transmit Byte Count LSB TXFP Transmit Byte Count TXFP Transmit Byte Count TXFP Transmit Byte Count MSB TXFP Transmit Frame Count LSB TXFP Transmit Frame Count TXFP Transmit Frame Count MSB TXFP Transmit User Aborted Frame Count LSB TXFP Transmit User Aborted Frame Count MSB TXFP Transmit Underrun Aborted Frame Count LSB TXFP Transmit Underrun Aborted Frame Count MSB WANS Configuration WANS Interrupt and Status WANS Phase Word LSB WANS Phase Word WANS Phase Word WANS Phase Word MSB WANS Reserved WANS Reserved WANS Reserved WANS Reference Period LSB WANS Reference Period MSB
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Address 0DB 0DC 0DD 0DE 0DF 0E0 0E1 0E2 0E3 0E4 0E5 0E6 0E7 0E8 0E9 0EA 0EB 0EC 0ED 0EE 0EF 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF 100 101 -1FF
Register Description WANS Phase Counter Period LSB WANS Phase Counter Period MSB WANS Phase Average Period WANS Reserved WANS Reserved RASE Interrupt Enable RASE Interrupt Status RASE Configuration/Control RASE SF BERM Accumulation Period LSB RASE SF BERM Accumulation Period RASE SF BERM Accumulation Period MSB RASE SF BERM Saturation Threshold LSB RASE SF BERM Saturation Threshold MSB RASE SF BERM Declaring Threshold LSB RASE SF BERM Declaring Threshold MSB RASE SF BERM Clearing Threshold LSB RASE SF BERM Clearing Threshold MSB RASE SD BERM Accumulation Period LSB RASE SD BERM Accumulation Period RASE SD BERM Accumulation Period MSB RASE SD BERM Saturation Threshold LSB RASE SD BERM Saturation Threshold MSB RASE SD BERM Declaring Threshold LSB RASE SD BERM Declaring Threshold MSB RASE SD BERM Clearing Threshold LSB RASE SD BERM Clearing Threshold MSB RASE Receive K1 RASE Receive K2 RASE Receive Z1/S1
Reserved
Reserved Reserved Reserved S/UNI-622-POS Concatenation Status and Enable S/UNI-622-POS Concatenation Interrupt Status Reserved Reserved S/UNI-622-POS Master Test Register Reserved for Test
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Notes on Register Memory Map: * * * For all register accesses, CSB must be low. Addresses that are not shown must be treated as Reserved. A[8] is the test resister select (TRS) and should be set low for normal mode register access.
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11 NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S/UNI-622-POS. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[8]) is low. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. All configuration bits that can be written into can also be read back. This allows the processor controlling the S/UNI-622-POS to determine the programming state of the block. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. Writing into read-only normal mode register bit locations does not affect S/UNI-622-POS operation unless otherwise noted. Performance monitoring counter registers are a common exception. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-622-POS operates as intended, reserved register bits must be written with their default value as indicated by the register bit description. Writing any data to the Master Reset and Identity register (0x00) simultaneously loads all the performance monitoring registers in RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP and TXFP blocks in the device. Writing any data to the performance register in question may individually trigger the performance registers in each block. In some cases, all performance registers in the block are loaded. In other cases, only the specific register being written will load. See the register descriptions for the performance register in question for more information.
2.
3. 4.
5.
6.
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Register 0x00: S/UNI-622-POS Master Reset and Identity Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R R R R R R R Function RESET TYPE[3] TYPE[2] TYPE[1] TYPE[0] ID[2] ID[1] ID[0] Default 0 0 0 1 1 0 1 0
This register allows the revision number of the S/UNI-622-POS to be read by software permitting graceful migration to newer, feature-enhanced versions of the S/UNI-622-POS. In addition, writing to this register simultaneously loads all the performance monitor registers in the RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks. ID[2:0]: The ID bits can be read to provide a binary S/UNI-622-POS revision number. TYPE[3:0]: The TYPE bits can be read to distinguish the S/UNI-622-POS from the other members of the S/UNI family of devices. RESET: The RESET bit allows the S/UNI-622-POS to be reset under software control. If the RESET bit is a logic one, the entire S/UNI-622-POS is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the S/UNI-622-POS out of reset. Holding the S/UNI-622-POS in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Otherwise, the effect of a software reset is equivalent to that of a hardware reset.
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x01: S/UNI-622-POS Master Configuration #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIP: The TIP bit is set to a logic one when the performance meter registers are being loaded. Writing to the S/UNI-622-POS Master Reset and Identity register initiates an accumulation interval transfer and loads all the performance meter registers in the RSOP, RLOP, RPOP, SSTB, SPTB, RXCP, TXCP, RXFP and TXFP blocks. TIP remains high while the transfer is in progress, and is set to a logic zero when the transfer is complete. TIP can be polled by a microprocessor to determine when the accumulation interval transfer is complete. PCM: The pointer concatenation mode select (PCM) determines the number of H1/H2 pointer pairs used to determine loss of pointer concatenation (LOPC) and pointer AIS (AISC). When PCM is set high, all H1/H2 pointer pairs are processed. When PCM is set low, only four H1/H2 pointer pairs (corresponding to the active STM-4-4c pointers) are processed. PDLE: The Parallel Diagnostic Loopback, PDLE bit enables the S/UNI-622-POS diagnostic loopback where the S/UNI-622-POS's Transmit Section Overhead Processor (TSOP) is directly connected to its Receive Section Overhead Processor (RSOP). When PDLE is logic one, loopback is enabled. Under this operating condition, the S/UNI-622-POS continues to operate normally in the transmit direction. When PDLE is logic zero, the S/UNI-622-POS operates normally in both directions. Type R/W R/W R/W R/W R/W R/W R/W R Function TPTBEN TSTBEN SDH_J0/Z0 TFPEN DLE PDLE PCM TIP Default 0 0 0 1 0 0 0 X
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111
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
DLE: The Diagnostic Loopback, DLE bit enables the S/UNI-622-POS diagnostic loopback where the S/UNI-622-POS's Transmit ATM and POS Processors (TXCP and TXFP respectively) are directly connected to the Receive ATM and POS Processor (RXCP and RXFP respectively). When DLE is logic one, loopback is enabled. Under this operating condition, the S/UNI-622-POS does not operate normally in the transmit direction or receive direction. When DLE is logic zero, the S/UNI-622-POS operates normally. TFPEN: The Transmit Frame Pulse Enable (TFPEN) enables the TFPI input. When TFPEN is set low, the TFPI input is disabled. When TFPEN is set high, the TFPI input is enabled. SDH_J0/Z0 The SDH_J0/Z0 bit selects whether to insert SONET or SDH format J0/Z0 section overhead bytes into the transmit stream. When SDH_J0/Z0 is set high, SDH format J0/Z0 bytes are selected for insertion. For this case, all the J0/Z0 bytes are forced to the value programmed in the S/UNI-622-POS Transmit J0/Z0 register. When SDH_J0/Z0 is set low, SONET format J0/Z0 bytes are selected for insertion. For this case, the J0/Z0 bytes of a STS-N signal are numbered incrementally from 1 to N. When SDH_J0/Z0 is set high, the transmit section trace buffer enable bit, TSTBEN can be used to overwrite the first J0/Z0 byte of a STS-N signal. TSTBEN: The TSTBEN bit controls whether the section trace message stored in the SSTB block is inserted into the transmit stream (i.e., the first J0/Z0 byte). When TSTBEN is set high and the SDH_J0/Z0 is set high, the message stored in the SSTB is inserted into the transmit stream. When TSTBEN is set low or SDH_J0/Z0 is set low, the section trace message is supplied by the TSOP block. TPTBEN: The TPTBEN bit controls whether the path trace message stored in the SPTB block is inserted into the transmit stream (i.e., the J1 byte). When TPTBEN is set high, the message stored in the SPTB is inserted into the transmit stream. When TPTBEN is set low, the path trace message is supplied by the TPOP block.
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112
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x02: S/UNI-622-POS Master Configuration #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOPFEBE The AUTOPFEBE bit determines if the remote path block errors are sent upon detection of an incoming path BIP error event. When AUTOPFEBE is set to logic one, one path FEBE is inserted for each path BIP error event, respectively. When AUTOPFEBE is set to logic zero, incoming path BIP error events do not generate FEBE events. AUTOLFEBE The AUTOLFEBE bit determines if remote line block errors are sent upon detection of an incoming line BIP error event. When AUTOLFEBE is set to logic one, one line FEBE is inserted for each line BIP error event, respectively. When AUTOLFEBE is set to logic zero, incoming line BIP error events do not generate FEBE events. AUTOPRDI The AUTOPRDI bit determines whether STS path remote defect indication (RDI) is sent immediately upon detection of an incoming alarm. When AUTOPRDI is set to logic one, STS path RDI is inserted immediately upon declaration of several alarms. Each alarm can individually be enabled and disabled using the S/UNI-622-POS Path RDI Control Registers. AUTOLRDI The AUTOLRDI bit determines if line remote defect indication (RDI) is sent immediately upon detection of an incoming alarm. When AUTOLRDI is set to logic one, line RDI is inserted immediately upon declaration of several alarms. Type R/W R/W R/W R/W R/W R/W R/W R/W Function SLLE SDLE LOOPT DPLE AUTOLRDI AUTOPRDI AUTOLFEBE AUTOPFEBE Default 0 0 0 0 1 1 1 1
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113
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Each alarm can individually be enabled and disabled using the S/UNI-622POS Line RDI Control Registers. DPLE: The Diagnostic Path Loopback, DPLE bit enables the S/UNI-622-POS diagnostic loopback where the S/UNI-622-POS's Transmit Path Overhead Processor (TPOP) is directly connected to its Receive Path Overhead Processor (RPOP). When DPLE is logic one, loopback is enabled. Under this operating condition, the S/UNI-622-POS continues to operates normally in the transmit direction. When DPLE is logic zero, the S/UNI-622-POS operates normally. LOOPT: The LOOPT bit selects the source of timing for the transmit section of the channel. When LOOPT is a logic zero, the transmitter timing is derived from input REFCLK (Clock Synthesis Unit). When LOOPT is a logic one, the transmitter timing is derived from the recovered clock (Clock Recovery Unit). LOOPT should not be set if the WANS is being used. The SDLE, SLLE or LOOPT bits should not be set high simultaneously. SDLE: The SDLE bit enables the serial diagnostic loopback. When SDLE is a logic one, the transmit serial stream on the TXD+/- differential outputs is internally connected to the received serial RXD+/- differential inputs. Under this operating condition, the S/UNI-622-POS continues to operates normally in the transmit direction. The SDLE, SLLE or LOOPT bits should not be set high simultaneously. SLLE: The SLLE bit enables the S/UNI-622-POS line loopback mode when the device is configured for 622.08 Mbit/s serial line interface mode of operation. When SLLE is a logic one, the recovered data from the receive serial RXD+/differential inputs is mapped to the TXD+/- differential outputs. Under this operating condition, the S/UNI-622-POS continues to operates normally in the receive direction. The SDLE, SLLE or LOOPT bits should not be set high simultaneously.
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114
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x03: S/UNI-622-POS Clock Monitors Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCLKA RCLKA RFCLKA TFCLKA Unused REFCLKA PICLKA PTCLKA Default X X X X X X X X
This register provides activity monitoring of the S/UNI-622-POS clocks. When a monitored clock signal makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read at periodic intervals to detect clock failures. PTCLKA: The PTCLK active (PTCLKA) bit monitors for low to high transition on the PTCLK parallel transmit clock input. PTCLKA is set high on a rising edge of PTCLK and is set low when this register is read. PICLKA: The PICLK active (PICLKA) bit monitors for low to high transition on the PICLK parallel receive clock input. PICLKA is set high on a rising edge of PICLK and is set low when this register is read. REFCLKA: The REFCLK active (REFCLKA) bit monitors for low to high transition on the REFCLK CSU-622 and CRU-622 reference clock input. REFCLKA is set high on a rising edge of REFCLK and is set low when this register is read.
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115
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
TFCLKA: The TFCLK active (TFCLKA) bit monitors for low to high transition on the TFCLK transmit system interface clock input. TFCLKI is set high on a rising edge of PTLCK and is set low when this register is read. RFCLKA: The RFCLK active (RFCLKA) bit monitors for low to high transition on the RFCLK receive system interface clock input. RFCLKA is set high on a rising edge of RFCLK and is set low when this register is read. RCLKA: The RCLK active (RCLKA) bit monitors for low to high transition on the RCLK receive line rate clock. RCLKA is set high on a rising edge of RCLK and is set low when this register is read. TCLKA: The TCLK active (TCLKA) bit monitors for low to high transition on the TCLK transmit line rate clock. TCLKA is set high on a rising edge of TCLK and is set low when this register is read.
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116
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x04: S/UNI-622-POS Master Interrupt Status #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused CONCATI RASEI TXCPI RXCPI RPOPI RLOPI RSOPI Default X X X X X X X X
When the interrupt output INTB goes low, this register allows the source of the active interrupt to be identified down to the block level. Further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. RSOPI: The RSOPI bit is high when an interrupt request is active from the RSOP block. The RSOP interrupt sources are enabled in the RSOP Control/Interrupt Enable Register. RLOPI: The RLOPI bit is high when an interrupt request is active from the RLOP block. The RLOP interrupt sources are enabled in the RLOP Interrupt Enable/Status Register. RPOPI: The RPOPI bit is high when an interrupt request is active from the RPOP block. The RPOP interrupt sources are enabled in the RPOP Interrupt Enable Register. RXCPI: The RXCPI bit is high when an interrupt request is active from the RXCP block. The RXCP interrupt sources are enabled in the RXCP Interrupt Enable/Status Register.
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117
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
TXCPI: The TXCPI bit is high when an interrupt request is active from the TXCP block. The TXCP interrupt sources are enabled in the TXCP Interrupt Control/Status Register. RASEI: The RASEI bit is high when an interrupt request is active from the RASE block. The RASE interrupt sources are enabled in the RASE Interrupt Enable Register. CONCATI: The CONCATI bit is high when an interrupt request is active from the Concatenation Interrupt Status Register. The CONCAT interrupt sources are enabled in the Concatenation Status and Enable Register.
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118
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x05: S/UNI-622-POS Master Interrupt Status #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function Reserved CSPII CRSII TXFPI RXFPI WANSI SSTBI SPTBI Default X X X X X X X X
When the interrupt output INTB goes low, this register allows the source of the active interrupt to be identified down to the block level. Further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. SPTBI: The SPTBI bit is a logic one when an interrupt request is active from the SPTB block. The SPTB interrupt sources are enabled in the SPTB Control Register and the SPTB Path Signal Label Status Register. SSTBI: The SSTBI bit is a logic one when an interrupt request is active from the SSTB block. The SSTB interrupt sources are enabled in the SSTB Control Register and the SSTB Synchronization Message Status Register. WANSI: The WANSI bit is a logic one when an interrupt request is active from the WANS block. The WANS interrupt sources are enabled in the WANS Interrupt Enable/Status Register. RXFPI: The RXFPI bit is high when an interrupt request is active from the RXFP block. The RXFP interrupt sources are enabled in the RXFP Interrupt Enable/Status Register.
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119
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
TXFPI: The TXFPI bit is high when an interrupt request is active from the TXFP block. The TXFP interrupt sources are enabled in the TXFP Interrupt Control/Status Register. CRSII: The CRSII bit is high when an interrupt request is active from the Clock Recovery and SIPO block (CRSI-622). The CRSI interrupt sources are enabled in the Clock Recovery Interrupt Control/Status Register. CSPII: The CSPII bit is high when an interrupt request is active from the Clock Synthesis and PISO block (CSPI-622). The CSPII interrupt sources are enabled in the Clock Synthesis Interrupt Control/Status Register.
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120
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x06: S/UNI-622-POS APS Configuration and Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type R/W R Function APSFRST APSI Unused APSFEBE APSRDI APSPD APSOE APSEN Default 0 X X 0 0 0 0 0
This register controls the APS transmit path override and the transmit path RDI and FEBE controls for 1+1 APS operation. See the Operation section for more discussion APSEN: The APSEN bit controls the 1+1 APS mode of the S/UNI-622-POS. When APSEN is set high, the S/UNI-622-POS transmit path data stream may be supplied to another S/UNI-622-POS using the POUT[7:0] bus. When APSEN is set low, the S/UNI-622-POS operates normally and POUT[7:0] is held at a constant value. APSOE: The APSOE bit controls the direction of the APS[4:0] pins. When APSOE is set low, the APS[4:0] pins are inputs and supply path RDI and FEBE information to TPOP. When APSEN is set high, the APS[4:0] pins are outputs and supply the receive path RDI and FEBE information from RPOP. APSPD: The APSPD bit controls overwriting of the transmit path data stream. When APSPD is set high, the transmit path data stream from TPOP is overwritten from the data sampled on the parallel input PIN[7:0] bus. A four-byte FIFO is used to handle minor phase variations between the transmit clock TCLK and the parallel input clock PICLK. When APSPD is set low, the TPOP path data stream is used.
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121
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
APSRDI: The APSRDI bit control the overwriting of the transmit path RDI values. When APSRDI is set high, the RDI information on the APS[4:0] pins is transmitted by TPOP. When APSRDI is set low, the RDI information from RPOP is transmitted by TPOP. The APSOE bit must be set low when APSRDI is set high. APSFEBE The APSFEBE bit controls the overwriting of the transmit path FEBE values. When APSFEBE is set high, the FEBE information on the APS[4:0] pins is transmitted by TPOP. When APSFEBE is set low, the FEBE information from RPOP is transmitted by TPOP. The APSOE bit must be set low when APSFEBE is set high. APSI: The APS FIFO interrupt indicates if the APS FIFO has underrun or overrun. The APSI register is set high when a FIFO underrun or overrun has occurred since the register was last read. The APSI register is set low when the register is read. This interrupt register should be periodically polled to ensure the APS FIFO is operating normally when configured for 1+1 APS operation. APSFRST: The APS FIFO Reset bit controls the four-byte FIFO which handles minor phase variations between the parallel input clock PTCLK and the transmit clock TCLK. When APSFRST is set high, the FIFO is held in reset. When APSFRST is set low, the FIFO may be reset during system reset. The APSFRST should be set high for at least 4 TCLK cycles when either S/UNI622-POS devices in the 1+1 APS configuration are reset.
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122
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x07: S/UNI-622-POS Miscellaneous Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXDINV: The receive inversion RXDINV controls the polarity of the receive data. When RXDINV is set high, the polarity of the RXD+/- is inverted. When RXDINV is set low, the RXD+/- inputs operate normally. RXDINV and TXDINV are ignored during line loopback operation (SLLE set high). TXDINV: The transmit inversion TXDINV controls the polarity of the transmit data. When TXDINV is set high, the polarity of the TXD+/- is inverted. When TXDINV is set low, the TXD+/- outputs operate normally. RXDINV and TXDINV are ignored during line loopback operation (SLLE set high). RSOC3: The Receive SONET/SDH OC3 enable allows the S/UNI-622-POS to process receive STS-3c/STM-1 data streams using the parallel line interface. When RSOC3 is set high, the SONET/SDH receive processors RSOP/RLOP/RPOP are configured for STS-3c/STM-1 operation. When RSOC3 is set low, the receive side of the S/UNI-622-POS is configured for STS-12c/STM-4-4c operation. Setting RSOC3 high when LIFSEL is low is invalid as the analog interface only operates at STS-12c/STM-4-4c line rates. R/W R/W R/W R/W R/W R/W Type Function Unused Unused TX_LIFINV RX_LIFINV TSOC3 RSOC3 TXDINV RXDINV Default X X 0 0 0 0 0 0
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123
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
TSOC3: The Transmit SONET/SDH OC3 enable allows the S/UNI-622-POS to process transmit STS-3c/STM-1 data streams using the parallel line interface. When TSOC3 is set high, the SONET/SDH transmit processors TSOP/TLOP/TPOP are configured for STS-3c/STM-1 operation. When TSOC3 is set low, the transmit side of the S/UNI-622-POS is configured for STS-12c/STM-1 operation. Setting TSOC3 high when LIFSEL is low is invalid as the analog interface only operates at STS-12c/STM-4-4c line rates. RX_LIFINV: The Receive LIFSEL Inversion select (RX_LIFINV) controls the interpretation of the LIFSEL pin for the receive side. When RX_LIFINV is set high, the polarity of the LIFSEL input is inverted. When RX_LIFINV is set low, the LIFSEL input operates normally for the receive side. TX_LIFINV: The Transmit LIFSEL Inversion select (TX_LIFINV) controls the interpretation of the LIFSEL pin for the transmit side. When TX_LIFINV is set high, the polarity of the LIFSEL input is inverted. When TX_LIFINV is set low, the LIFSEL input operates normally for the transmit side.
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124
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x08: S/UNI-622-POS Auto Line RDI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W Function SDLRDI SFLRDI LOFLRDI LOSLRDI RTIMLDRI RTIULRDI LAISLRDI Unused Default 0 0 1 1 0 0 1 X
This register controls the auto assertion of the line RDI in TLOP for the entire SONET/SDH stream. LAISLRDI: The Line Alarm Indication Signal LRDI (LAISLRDI) controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition. When LAISLRDI is set high, the transmit line RDI will be inserted. When LAISLRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high. RTIULRDI: The Section Trace Identifier Unstable LRDI (RTIULRDI) controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition. When RTIULRDI is set high, the transmit line RDI will be inserted. When RTIULRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high. RTIMLRDI: The Section Trace Identifier Mismatch LRDI (RTIMLRDI) controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition. When RTIMLDRI is set high, the transmit line RDI will be inserted. When RTIMLDRI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high.
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125
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
LOSLRDI: The Loss of Signal LRDI (LOSLRDI) controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition. When LOSLRDI is set high, the transmit line RDI will be inserted. When LOSLRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high. LOFLRDI: The Loss of Frame LRDI (LOFLRDI) controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition. When LOFLRDI is set high, the transmit line RDI will be inserted. When LOFLRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high. SFLRDI: The Signal Fail BER LRDI (SFLRDI) controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition. When SFLRDI is set high, the transmit line RDI will be inserted. When SFLRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high. SDLRDI: The Signal Degrade BER LRDI (SDLRDI) controls the insertion of a Line RDI in the transmit data stream upon detection of this alarm condition. When SDLRDI is set high, the transmit line RDI will be inserted. When SDLRDI is set low, no action is taken. This register bit is used only if the AUTOLRDI register bit is also set high.
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126
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x09: S/UNI-622-POS Auto Path RDI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LCDPRDI ALRMPRDI PAISPRDI PSLMPRDI LOPPRDI LOPCONPRDI PTIUPRDI PTIMPRDI Default 0 0 1 1 1 1 1 1
This register controls the auto assertion of path RDI (G1 bit 5) in the TPOP for the entire SONET/SDH stream. Also see the Auto Enhanced Path RDI register. PTIMPRDI: The Path Trace Identifier Mismatch PRDI (PTIMPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition. When PTIMPRDI is set high, the transmit line RDI will be inserted. When PTIMPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high. PTIUPRDI: The Path Trace Identifier Unstable PRDI (PTIUPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition. When PTIUPRDI is set high, the transmit line RDI will be inserted. When PTIUPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high. LOPCONPRDI: The Loss of Pointer Concatenation Indication PRDI (LOPCONPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition. When LOPCONPRDI is set high, the transmit line RDI will be inserted. When LOPCONPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high.
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127
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
LOPPRDI: The Loss of Pointer Indication PRDI (LOPPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition. When LOPPRDI is set high, the transmit line RDI will be inserted. When LOPPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high. PSLMPRDI: The Path Signal Label Mismatch PRDI (PSLMPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition. When PSLMPRDI is set high, the transmit line RDI will be inserted. When PSLMPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high. PAISPRDI: The Path Alarm Indication Signal PRDI (PAISPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition. When PAISPRDI is set high, the transmit line RDI will be inserted. When PAISPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high. ALRMPRDI: The Line Alarm Indication Signal PRDI (ALRMPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of one of the following alarm conditions: Loss of Signal (LOS), Loss of Frame (LOF) and Line Alarm Indication Signal (LAIS). When ALRMPRDI is set high, the transmit line RDI will be inserted When ALRMPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high. LCDPRDI: The Loss of ATM Cell Delineation Signal PRDI (LCDPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm. When LCDPRDI is set high, the transmit path RDI will be inserted. When LCDPRDI is set low, no action is taken. This register bit is used only if the AUTOPRDI register bit is also set high.
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Register 0x0A: S/UNI-622-POS Auto Enhanced Path RDI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LCDEPRDI NOALMEPRDI NOPAISEPRDI PSLMEPRDI NOLOPEPRDI
NOLOPCONEPRDI
Default 0 0 0 1 0 0 0 1
TIUEPRDI TIMEPRDI
This register controls the auto assertion of enhanced path RDI (G1 bit 5, 6 and 7) in the TPOP for the entire SONET/SDH stream. TIMEPRDI: When set high, the TIMEPRDI bit enables enhanced path RDI assertion when path trace message mismatch (TIM) events are detected in the receive stream. When TIMEPRDI is set high and TIM occurs, bit 6 of the G1 byte is set high while bit 7 of the G1 byte is set low. When TIMEPRDI is set low, trace identifier mismatch events have no effect on path RDI. In addition, this bit has no effect when EPRDI_EN is set low. TIUEPRDI: When set high, the TIUEPRDI bit enables enhanced path RDI assertion when path trace message unstable events are detected in the receive stream. When TIUEPRDI is set high and path trace message unstable occurs, bit 6 of the G1 byte is set high while bit 7 of the G1 byte is set low. When TIUEPRDI is set low, trace identifier unstable events have no effect on path RDI. In addition, this bit has no effect when EPRDI_EN is set low. NOLOPCONEPRDI: When set high, the NOLOPCONEPRDI bit disables enhanced path RDI assertion when loss of pointer concatenation (LOPCON) events are detected in the receive stream. When NOLOPCONEPRDI is set high and LOPCON occurs, bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
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NOLOPCONEPRDI has precedence over PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI. When NOLOPCONEPRDI is set low, reporting of enhanced RDI is according to PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated alarm states. NOLOPEPRDI: When set high, the NOLOPEPRDI bit disables enhanced path RDI assertion when loss of pointer (LOP) events are detected in the receive stream. When NOLOPEPRDI is set high and LOP occurs, bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high. NOLOPEPRDI has precedence over PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI. When NOLOPEPRDI is set low, reporting of enhanced RDI is according to PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated alarm states. PSLMEPRDI: When set high, the PSLMEPRDI bit enables enhanced path RDI assertion when path signal label mismatch (PSLM) events are detected in the receive stream. When PSLMEPRDI is set high and PSLM occurs, bit 6 of the G1 byte is set high while bit 7 of the G1 byte is set low. When PSLMEPRDI is set low, path signal label mismatch events have no effect on path RDI. In addition, this bit has no effect when EPRDI_EN is set low. NOPAISEPRDI: When set high, the NOPAISEPRDI bit disables enhanced path RDI assertion when the path alarm indication signal state (PAIS) is detected in the receive stream. When NOPAISEPRDI is set high and PAIS occurs, bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high. NOPAISEPRDI has precedence over PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI. When NOPAISEPRDI is set low, reporting of enhanced RDI is according to PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated alarm states. NOALMEPRDI: When set high, the NOALMEPRDI bit disables enhanced path RDI assertion when loss of signal (LOS), loss of frame (LOF) or line alarm indication signal (LAIS) events are detected in the receive stream. When NOALMEPRDI is set
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high and one of the listed events occur, bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high. NOALMEPRDI has precedence over PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI. When NOALMEPRDI is set low, reporting of enhanced RDI is according to PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated alarm states. LCDEPRDI: When set high, the LCDEPRDI bit enables enhanced path RDI assertion when loss of ATM cell delineation (LCD) events are detected in the receive stream. If enabled, when the event occurs, bit 6 of the G1 byte is set high while bit 7 of the G1 byte is set low. When LCDEPRDI is set low, loss of ATM cell delineation has no effect on path RDI. In addition, this bit has no effect when EPRDI_EN is set low.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x0B: S/UNI-622-POS Receive RDI and Enhanced RDI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type R/W R/W Function PAISCONPRDI
NOPAISCONEPRDI
Default 0 0 X X X 0 1 1
Unused Unused Unused EPRDI_EN UNEQPRDI UNEQEPRDI
This register along with the Enhanced Path RDI Control register controls the auto assertion of path RDI (G1 bit 5, 6 and 7) in the TPOP for the entire SONET/SDH stream. UNEQEPRDI: When set high, the UNEQEPRDI bit enables enhanced path RDI assertion when the path signal label in the receive stream indicates unequipped status. When UNEQEPRDI is set high and the path signal label indicates unequipped, bit 6 of the G1 byte is set high while bit 7 of the G1 byte is set low. When UNEQEPRDI is set low, path signal label unequipped status has no effect on enhanced path RDI. UNEQPRDI: When set high, the UNEQPRDI bit enables path RDI assertion when the path signal label in the receive stream indicates unequipped status. When UNEQPRDI is set low, the path signal label unequipped status has no effect on path RDI. EPRDI_EN: The EPRDI_EN bit enables the automatic insertion of enhanced RDI in the local transmitter. When EPRDI_EN is a logic one, auto insertion is enabled using the event enable bits in this register. When EPRDI_EN is a logic zero, enhanced path RDI is not automatically inserted in the transmit stream.
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NOPAISCONEPRDI: When set high, the NOPAISCONEPRDI bit disables enhanced path RDI assertion when path AIS concatenation (PAISCON) events are detected in the receive stream. When NOPAISCONEPRDI is set high and PAISCON occurs, bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set high. NOPAISCONEPRDI has precedence over PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI. When NOPAISCONEPRDI is set low, reporting of enhanced RDI is according to PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated alarm states. PAISCONPRDI: When set high, the PAISCONPRDI bit enables path RDI assertion when path AIS concatenation (PAISCON) events are detected in the receive stream. When PAISCONPRDI is set low, path AIS concatenation events have no effect on path RDI.
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x0C: S/UNI-622-POS Received Line AIS Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Type R/W R/W R/W R/W R/W R/W Function SDINS SFINS LOFINS LOSINS RTIMINS RTIUINS Unused DCCAIS Default 0 0 1 1 0 0 X 0
This register controls the auto assertion of the receive line AIS for the entire SONET/SDH stream. DCCAIS: The DCCAIS bit enables the insertion of all ones in the section DCC (RSLD) and the line DCC (RLD) when loss of frame (LOF) or LOS is declared. When DCCAIS is a logic one, all ones is inserted in RSLD and RLD when LOF or LOS is declared. RTIUINS: The RTIUINS bit enables the insertion of path AIS in the receive direction upon the declaration of section trace unstable. If RTIUINS is a logic one, path AIS is inserted into the SONET/SDH frame when the current received section trace identifier message has not matched the previous message for eight consecutive messages. Path AIS is terminated when the current message becomes the accepted message. RTIMINS: The RTIMINS bit enables the insertion of path AIS in the receive direction upon the declaration of section trace mismatch. If RTIMINS is a logic one, path AIS is inserted into the SONET/SDH frame when the accepted identifier message differs from the expected message. Path AIS is terminated when the accepted message matches the expected message.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
LOSINS: The LOSINS bit enables the insertion of path AIS in the receive direction upon the declaration of loss of signal (LOS). If LOSINS is a logic one, path AIS is inserted into the SONET/SDH frame when LOS is declared. Path AIS is terminated when LOS is removed. LOFINS: The LOFINS bit enables the insertion of path AIS in the receive direction upon the declaration of loss of frame (LOF). If LOFINS is a logic one, path AIS is inserted into the SONET/SDH frame when LOF is declared. Path AIS is terminated when LOF is removed. SFINS: The SFINS bit enables the insertion of path AIS in the receive direction upon the declaration of signal fail (SF). If SFINS is a logic one, path AIS is inserted into the SONET/SDH frame when SF is declared. Path AIS is terminated when SF is removed. SDINS: The SDINS bit enables the insertion of path AIS in the receive direction upon the declaration of signal degrade (SD). If SDINS is a logic one, path AIS is inserted into the SONET/SDH frame when SD is declared. Path AIS is terminated when SD is removed.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x0D: S/UNI-622-POS Receive Path AIS Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PAISCONPAIS LOPCONPAIS PSLUPAIS PSLMPAIS LOPPAIS Reserved TIUPAIS TIMPAIS Default 1 1 1 1 1 1 1 1
This register controls the auto assertion of path AIS, which will force a loss of cell delineation by the receive cell processor. TIMPAIS: When set high, the TIMPAIS bit enables path AIS insertion when path trace message mismatch (TIM) events are detected in the receive stream. When TIMPAIS is set low, trace identifier mismatch events will not assert path AIS. TIUPAIS: When set high, the TIUPAIS bit enables path AIS insertion when path trace message unstable events are detected in the receive stream. When TIUPAIS is set low, trace identifier unstable events will not assert path AIS. LOPPAIS: When set high, the LOPPAIS bit enables path AIS insertion when loss of pointer (LOP) events are detected in the receive stream. When LOPPAIS is set low, loss of pointer events will not assert path AIS. PSLMPAIS: When set high, the PSLMPAIS bit enables path AIS insertion when path signal label mismatch (PSLM) events are detected in the receive stream. When PSLMPAIS is set low, path signal label mismatch events will not assert path AIS.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
PSLUPAIS: When set high, the PSLUPAIS bit enables path AIS insertion when path signal label unstable (PSLU) events are detected in the receive stream. When PSLUPAIS is set low, path signal label unstable events will not assert path AIS. LOPCONPAIS: When set high, the LOPCONPAIS bit enables path AIS insertion when loss of pointer concatenation (LOPCON) events are detected in the receive stream. When LOPCONPAIS is set low, loss of pointer concatenation events will not assert path AIS. PAISCONPAIS: When set high, the PAISCONPAIS bit enables path AIS insertion when Path AIS concatenation (PAISCON) events are detected in the receive direction. When PAISCONPAIS is set low, Path AIS concatenation events will not assert path AIS. Reserved: The reserved bit must be programmed to logic zero for proper operation.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x0E: S/UNI-622-POS Receive Alarm Control #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function CONEN PTIMEN PSLMEN PERDIEN PRDIEN PAISEN LCDEN LOPEN Default 0 0 0 0 0 0 0 0
Register 0x0F: S/UNI-622-POS Receive Alarm Control #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function STIMEN SFBEREN SDBEREN LRDIEN LAISEN OOFEN LOFEN LOSEN Default 0 0 0 0 0 0 0 0
LOSEN, LOFEN, OOFEN, LAISEN, LRDIEN, SDBEREN, SFBEREN, STIMEN, LOPEN, LCDEN, PAISEN, PRDIEN, PERDIEN, PSLMEN, PTIMEN, CONEN: The above enable bits allow the corresponding alarm indications to be reported (ORed) into the RALRM output. When the enable bit is high, the corresponding alarm indication is combined with other alarm indications and output on RALRM. When the enable bit is low, the corresponding alarm indication does not affect the RALRM output.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Alarm LOS LOF OOF LAIS LRDI SDBER SFBER STIM LOP LCD PAIS PRDI PERDI PSLM PTIM CON Reserved:
Description Loss of signal Loss of frame Out of Frame Line Alarm Indication Signal Line Remote Defect Indication Signal Degrade Bit Error Rate Signal Fail Bit Error Rate Section Trace Identifier Mismatch Loss of Pointer Loss of Cell Delineation Path Alarm Indication Signal Path Remote Defect Indication Path Enhanced Remote Defect Indication Path Signal Label Mismatch Path Trace Identifier Mismatch Pointer Concatenation Violation or Pointer AIS
The reserved bit must be programmed to logic zero for proper operation.
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139
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x10: RSOP Control/Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFE: The OOFE bit is an interrupt enable for the out-of-frame alarm. When OOFE is set to logic one, an interrupt is generated when the out-of-frame alarm changes state. LOFE: The LOFE bit is an interrupt enable for the loss of frame alarm. When LOFE is set to logic one, an interrupt is generated when the loss of frame alarm changes state. LOSE: The LOSE bit is an interrupt enable for the loss of signal alarm. When LOSE is set to logic one, an interrupt is generated when the loss of signal alarm changes state. BIPEE: The BIPEE bit is an interrupt enable for the section BIP-8 errors. When BIPEE is set to logic one, an interrupt is generated when a section BIP-8 error (B1) is detected. ALGO2: The ALGO2 bit position selects the framing algorithm used to determine and maintain the frame alignment. When a logic one is written to the ALGO2 bit position, the framer is enabled to use the second of the framing algorithms where only the first A1 framing byte and the first 4 bits of the last A2 framing Type R/W R/W W R/W R/W R/W R/W R/W Function BLKBIP DDS FOOF ALGO2 BIPEE LOSE LOFE OOFE Default 0 0 X 0 0 0 0 0
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140
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
byte (12 bits total) are examined. This algorithm examines only 12 bits of the framing pattern regardless; all other framing bits are ignored. When a logic zero is written to the ALGO2 bit position, the framer is enabled to use the first of the framing algorithms where all the A1 framing bytes and all the A2 framing bytes are examined. FOOF: The FOOF bit controls the framing of the RSOP. When a logic one is written to FOOF, the RSOP is forced out of frame at the next frame boundary. The FOOF bit is a write only bit. Register reads may yield a logic one or a logic zero. DDS: The DDS bit is set to logic one to disable the descrambling of the STS12c/STM-4-4c stream. When DDS is a logic zero, descrambling is enabled. BLKBIP: The BLKBIP bit position enables the accumulating of section BIP word errors. When a logic one is written to the BLKBIP bit position, one or more errors in the BIP-8 byte result in a single error being accumulated in the B1 error counter. When a logic zero is written to the BLKBIP bit position, all errors in the B1 byte are accumulated in the B1 error counter.
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141
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x11: RSOP Status/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFV: The OOFV bit is read to determine the out-of-frame state of the RSOP. When OOFV is high, the RSOP is out of frame. When OOFV is low, the RSOP is in-frame. LOFV: The LOFV bit is read to determine the loss of frame state of the RSOP. When LOFV is high, the RSOP has declared loss of frame. LOSV: The LOSV bit is read to determine the loss of signal state of the RSOP. When LOSV is high, the RSOP has declared loss of signal. OOFI: The OOFI bit is the out-of-frame interrupt status bit. OOFI is set high when a change in the out-of-frame state occurs. This bit is cleared when this register is read. LOFI: The LOFI bit is the loss of frame interrupt status bit. LOFI is set high when a change in the loss of frame state occurs. This bit is cleared when this register is read. R R R R R R R Type Function Unused BIPEI LOSI LOFI OOFI LOSV LOFV OOFV Default X X X X X X X X
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
LOSI: The LOSI bit is the loss of signal interrupt status bit. LOSI is set high when a change in the loss of signal state occurs. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is set high when a section layer (B1) bit error is detected. This bit is cleared when this register is read.
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143
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x12: RSOP Section BIP-8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function SBE[7] SBE[6] SBE[5] SBE[4] SBE[3] SBE[2] SBE[1] SBE[0] Default X X X X X X X X
Register 0x13: RSOP Section BIP-8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBE[15:0]: Bits SBE[15:0] represent the number of section BIP-8 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RSOP Section BIP-8 Register addresses. Such a write transfers the internally accumulated error count to the Section BIP-8 registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. Type R R R R R R R R Function SBE[15] SBE[14] SBE[13] SBE[12] SBE[11] SBE[10] SBE[9] SBE[8] Default X X X X X X X X
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
The count can also be polled by writing to the S/UNI-622-POS Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks.
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145
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x14: TSOP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LAIS: The LAIS bit controls the insertion of line alarm indication signal (AIS). When LAIS is set to logic one, the TSOP inserts AIS into the transmit SONET/SDH stream. Activation or deactivation of line AIS insertion is synchronized to frame boundaries. Line AIS insertion results in all bits of the SONET/SDH frame being set to 1 prior to scrambling except for the section overhead. DS: The DS bit is set to logic one to disable the scrambling of the STS-12c/STM4-4c stream. When DS is a logic zero, scrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R/W R/W R/W R/W R/W Type Function Unused DS Reserved Reserved Reserved Reserved Reserved LAIS Default X 0 0 0 0 0 0 0
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x15: TSOP Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DFP: The DFP bit controls the insertion of a single bit error continuously in the most significant bit (bit 1) of the A1 section overhead framing byte. When DFP is set to logic one, the A1 bytes are set to 0x76 instead of 0xF6. DBIP8: The DBIP8 bit controls the insertion of bit errors continuously in the section BIP-8 byte (B1). When DBIP8 is set to logic one, the B1 byte is inverted. DLOS: The DLOS bit controls the insertion of all zeros in the STS-12c/STM-4-4c stream. When DLOS is set to logic one, the transmit stream is forced to 0x00. R/W R/W R/W Type Function Unused Unused Unused Unused Unused DLOS DBIP8 DFP Default X X X X X 0 0 0
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x18: RLOP Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDIV: The LRDIV bit is read to determine the remote defect indication state of the RLOP. When LRDIV is high, the RLOP has declared line RDI. LAISV: The LAISV bit is read to determine the line AIS state of the RLOP. When LAISV is high, the RLOP has declared line AIS. FEBEWORD: The FEBEWORD bit controls the accumulation of FEBEs. When FEBEWORD is high, if the FEBE event has a value from 1 to 4, the FEBE event counter is incremented for each and every FEBE bit. However, if the FEBE event has a value greater than 4 and is valid, the FEBE event counter is incremented by 4. When FEBEWORD is low, the FEBE event counter is incremented for each and every FEBE bit that occurs during that frame (the counter can be incremented up to 24.). BIPWORDO: The BIPWORDO bit controls the indication of B2 errors reported to the TLOP block for insertion as FEBEs. When BIPWORDO is logic one, the BIP errors are indicated once per frame whenever one or more B2 bit errors occur during that frame. When BIPWORDO is logic zero, BIP errors are indicated once for every B2 bit error that occurs during that frame. The accumulation of B2 error events functions independently and is controlled by the BIPWORD register bit. Type R/W R/W R/W R/W R/W R/W R R Function BIPWORD ALLONES AISDET LRDIDET BIPWORDO FEBEWORD LAISV LRDIV Default 0 0 0 0 0 0 X X
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LRDIDET: The LRDIDET bit determines the line RDI alarm detection algorithm. When LRDIDET is set to logic one, line RDI is declared when a 110 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for three consecutive frames. When LRDIDET is set to logic zero, line RDI is declared when a 110 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for five consecutive frames. AISDET: The AISDET bit determines the line AIS alarm detection algorithm. When AISDET is set to logic one, line AIS is declared when a 111 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for three consecutive frames. When AISDET is set to logic zero, line AIS is declared when a 111 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for five consecutive frames. ALLONES: The ALLONES bit controls automatically forcing the SONET/SDH frame passed to downstream blocks to logical all-ones whenever line AIS is detected. When ALLONES is set to logic one, the SONET/SDH frame is forced to logic one immediately when the line AIS alarm is declared. When line AIS is removed, the downstream data stream is immediately returned to carrying the receive data. When ALLONES is set to logic zero, the downstream data stream always carries the receive data regardless of the line AIS alarm state. BIPWORD: The BIPWORD bit controls the accumulation of B2 errors. When BIPWORD is logic one, the B2 error event counter is incremented only once per frame whenever one or more B2 bit errors occur during that frame. When BIPWORD is logic zero, the B2 error event counter is increment for each and every B2 bit error that occurs during that frame.
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
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Register 0x19: RLOP Interrupt Enable/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDII: The LRDII bit is the remote defect indication interrupt status bit. LRDII is set high when a change in the line RDI state occurs. This bit is cleared when this register is read. LAISI: The LAISI bit is the line AIS interrupt status bit. LAISI is set high when a change in the line AIS state occurs. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the line BIP-96 interrupt status bit. BIPEI is set high when a line layer (B2) bit error is detected. This bit is cleared when this register is read. FEBEI: The FEBEI bit is the line far end block error interrupt status bit. FEBEI is set high when a line layer FEBE (M1) is detected. This bit is cleared when this register is read. LRDIE: The LRDIE bit is an interrupt enable for the line remote defect indication alarm. When LRDIE is set to logic one, an interrupt is generated when the line RDI state changes. Type R/W R/W R/W R/W R R R R Function FEBEE BIPEE LAISE LRDIE FEBEI BIPEI LAISI LRDII Default 0 0 0 0 X X X X
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LAISE: The LAISE bit is an interrupt enable for line AIS. When LAISE is set to logic one, an interrupt is generated when line AIS changes state. BIPEE: The BIPEE bit is an interrupt enable for the line BIP-96 errors. When BIPEE is set to logic one, an interrupt is generated when a line BIP-96 error (B2) is detected. FEBEE: The FEBEE bit is an interrupt enable for the line far end block errors. When FEBEE is set to logic one, an interrupt is generated when FEBE (Z2) is detected.
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PMC-Sierra, Inc.
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Register 0x1A: RLOP Line BIP-96 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LBE[7] LBE[6] LBE[5] LBE[4] LBE[3] LBE[2] LBE[1] LBE[0] Default X X X X X X X X
Register 0x1B: RLOP Line BIP-96 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LBE[15] LBE[14] LBE[13] LBE[12] LBE[11] LBE[10] LBE[9] LBE[8] Default X X X X X X X X
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Register 0x1C: RLOP Line BIP-96 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LBE[19:0] Bits LBE[19:0] represent the number of line BIP-96 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to any of the RLOP Line BIP-96 Register or Line FEBE Register addresses. Such a write transfers the internally accumulated error count to the Line BIP-96 Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. The count can also be polled by writing to the S/UNI-622-POS Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP and TXFP blocks. R R R R Type Function Unused Unused Unused Unused LBE[19] LBE[18] LBE[17] LBE[16] Default X X X X X X X X
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Register 0x1D: RLOP Line FEBE LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LFE[7] LFE[6] LFE[5] LFE[4] LFE[3] LFE[2] LFE[1] LFE[0] Default X X X X X X X X
Register 0x1E: RLOP Line FEBE Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LFE[15] LFE[14] LFE[13] LFE[12] LFE[11] LFE[10] LFE[9] LFE[8] Default X X X X X X X X
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Register 0x1F: RLOP Line FEBE MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFE[19:0] Bits LFE[19:0] represent the number of line FEBE errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to any of the RLOP Line BIP-96 Register or Line FEBE Register addresses. Such a write transfers the internally accumulated error count to the Line FEBE Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. The count can also be polled by writing to the S/UNI-622-POS Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP and TXFP blocks. R R R R Type Function Unused Unused Unused Unused LFE[19] LFE[18] LFE[17] LFE[16] Default X X X X X X X X
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Register 0x20: TLOP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDI: The LRDI bit controls the insertion of line remote defect indication (LRDI). When LRDI is set to logic one, the TLOP inserts line RDI into the transmit SONET/SDH stream. Line RDI is inserted by transmitting the code 110 in bit positions 6, 7 and 8 of the K2 byte of the STS-12c stream. APSREG: The APSREG bit selects the source for the transmit APS channel K1/K2 bytes. When APSREG is a logic zero, 0x0000 is inserted in the transmit APS K1 and K2 bytes. When APSREG is a logic one, the transmit APS channel is inserted from the TLOP Transmit K1 Register and the TLOP Transmit K2 Register. Reserved: The reserved bits must be programmed to logic zero for proper operation. Type R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved Reserved APSREG Reserved Reserved Reserved Reserved LRDI Default 0 0 0 0 0 0 0 0
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Register 0x21: TLOP Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBIP96: The DBIP96 bit controls the insertion of bit errors continuously in the line BIP96 bytes (B2). When DBIP96 is set to logic one, the B2 bytes are inverted. R/W Type Function Unused Unused Unused Unused Unused Unused Unused DBIP96 Default X X X X X X X 0
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Register 0x22: TLOP Transmit K1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K1[7:0]: The K1[7:0] bits contain the value inserted in the K1 byte when the APSREG bit in the TLOP Control Register is logic one. K1[7] is the most significant bit corresponding to bit 1, the first bit transmitted. K1[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. The bits in this register are double buffered so that register writes do not need to be synchronized to SONET/SDH frame boundaries. The insertion of a new APS code value is initiated by a write to this register. The contents of this register, and the TLOP Transmit K2 Register are inserted in the SONET/SDH stream starting at the next frame boundary. Successive writes to this register must be spaced at least two frames (250 s) apart. Type R/W R/W R/W R/W R/W R/W R/W R/W Function K1[7] K1[6] K1[5] K1[4] K1[3] K1[2] K1[1] K1[0] Default 0 0 0 0 0 0 0 0
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Register 0x23: TLOP Transmit K2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K2[7:0]: The K2[7:0] bits contain the value inserted in the K2 byte when the APSREG bit in the TLOP Control Register is logic one. K2[7] is the most significant bit corresponding to bit 1, the first bit transmitted. K2[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. The bits in this register are double buffered so that register writes do not need to be synchronized to SONET/SDH frame boundaries. The insertion of a new APS code value is initiated by a write to the TLOP Transmit K1 Register. A coherent APS code value is ensured by writing the desired K2 APS code value to this register before writing the TLOP Transmit K1 Register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function K2[7] K2[6] K2[5] K2[4] K2[3] K2[2] K2[1] K2[0] Default 0 0 0 0 0 0 0 0
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Register 0x24: S/UNI-622-POS Transmit Sync. Message (S1) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TS1[3:0]: The value written to these bit positions is inserted in the first S1 byte position of the transmit stream. The S1 byte is used to carry synchronization status messages between line terminating network elements. TS1[3] is the most significant bit, corresponding to the first bit transmitted. TS1[0] is the least significant bit, corresponding to the last bit transmitted. Reserved: The reserved bits must be programmed to logic zero for proper operation. Type R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved Reserved Reserved Reserved TS1[3] TS1[2] TS1[1] TS1[0] Default 0 0 0 0 0 0 0 0
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Register 0x25: S/UNI-622-POS Transmit J0/Z0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 J0/Z0[7:0]: The value written to this register is inserted into the J0/Z0 byte positions of the transmit stream when enabled using the SDH_J0/Z0 register. J0/Z0[7] is the most significant bit, corresponding to the first bit (bit 1) transmitted. J0/Z0[0] is the least significant bit, corresponding to the last bit (bit 8) transmitted. Type R/W R/W R/W R/W R/W R/W R/W R/W Function J0/Z0[7] J0/Z0[6] J0/Z0[5] J0/Z0[4] J0/Z0[3] J0/Z0[2] J0/Z0[1] J0/Z0[0] Default 1 1 0 0 1 1 0 0
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Register 0x28: SSTB Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ZEROEN RRAMACC RTIUIE RTIMIE PER5 TNULL NOSYNC LEN16 Default 0 0 0 0 0 1 0 0
This register controls the receive and transmit portions of the SSTB. LEN16: The section trace message length bit (LEN16) selects the length of the section trace message to be 16 bytes or 64 bytes. When set high, a 16-byte section trace message is selected. If set low, a 64-byte section trace message is selected. NOSYNC: The section trace message synchronization disable bit (NOSYNC) disables the writing of the section trace message into the trace buffer to be synchronized to the content of the message. When LEN16 is set high and NOSYNC is set low, the receive section trace message byte with its most significant bit set will be written to the first location in the buffer. When LEN16 is set low, and NOSYNC is also set low, the byte after the carriage return/linefeed (CR/LF) sequence will be written to the first location in the buffer. When NOSYNC is set high, synchronization is disabled, and the section trace message buffer behaves as a circular buffer. TNULL: The transmit null bit (TNULL) controls the insertion of an all-zeros section trace identifier message in the transmit stream. When TNULL is set high, the contents of the transmit buffer is ignored and all-zeros bytes are provided to the TSOP block. When TNULL is set low the contents of the transmit section trace buffer is sent to TSOP for insertion into the J0/Z0 transmit section
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overhead byte. TNULL should be set high before changing the contents of the trace buffer to avoid sending partial messages. PER5: The receive trace identifier persistence bit (PER5) controls the number of times a section trace identifier message must be received unchanged before being accepted. When PER5 is set high, a message is accepted when it is received unchanged five times consecutively. When PER5 is set low, the message is accepted after three identical repetitions. RTIMIE: The RTIMIE bit controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state. When RTIMIE is a logic one, changes in match state activates the interrupt (INTB) output. RTIUIE: The RTIUIE bit controls the activation of the interrupt output when the receive identifier message changes state. When RTIUIE is a logic one, changes in the received section trace identifier message stable/unstable state will activate the interrupt (INTB) output. RRAMACC: The receive RAM access control bit (RRAMACC) directs read and writes access to between the receive and transmit portion of the S/UNI-622-POS. When RRAMACC is set high, subsequent microprocessor read and write accesses are directed to the receive side trace buffers. When RRAMACC is set low, microprocessor accesses are directed to the transmit side trace buffer. ZEROEN: The zero enable bit (ZEROEN) enables TIM assertion and removal based on an all ZERO's section trace message string. When ZEROEN is set high, all ZERO's section trace message strings are considered when entering and exiting TIM states. When ZEROEN is set low, all ZERO's section trace message strings are ignored. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x29: SSTB Section Trace Identifier Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R Function BUSY Unused Unused Unused RTIUI RTIUV RTIMI RTIMV Default 0 X X X X X X X
This register reports the section trace identifier status of the SSTB. RTIMV: The RTIMV bit reports the match/mismatch status of the identifier message framer. RTIMV is a logic one when the accepted identifier message differs from the expected message written by the microprocessor. RTIMV is a logic zero when the accepted message matches the expected message. RTIMI: The RTIMI bit is a logic one when match/mismatch status of the trace identifier framer changes state. This bit is cleared when this register is read. RTIUV: The RTIUV bit reports the stable/unstable status of the identifier message framer. RTIUV is a logic one when the current received section trace identifier message has not matched the previous message for eight consecutive messages. RTIUV is a logic zero when the current message becomes the accepted message as determined by the PER5 bit in the SPTB Control register. RTIUI: The RTIUI bit is a logic one when stable/unstable status of the trace identifier framer changes state. This bit is cleared when this register is read.
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BUSY: The BUSY bit reports whether a previously initiated indirect read or write to a message buffer has been completed. BUSY is set high upon writing to the SSTB Indirect Address register, and stays high until the initiated access has completed, at which point BUSY is set low. This register should be polled to determine when new data is available in the SSTB Indirect Data register.
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Register 0x2A: SSTB Indirect Address Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0] Default 0 0 0 0 0 0 0 0
This register supplies the address used to index into section trace identifier buffers. A[6:0]: The indirect read address bits (A[6:0]) indexes into the section trace identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference the receive capture page while addresses 64 to 127 reference the receive expected page. The receive capture page contains the identifier bytes extracted from the receive stream. The receive expected page contains the expected trace identifier message downloaded from the microprocessor. When RRAMACC is set low, addresses 0 to 63 reference the transmit message buffer which contains the identifier message to be inserted in the section trace byte, the first J0/Z0 byte, of each frame in the transmit stream. When RRAMACC is set low, addresses 64 to 127 are unused and must not be accessed. RWB: The access control bit (RWB) selects between an indirect read or write access to the static page of the section trace message buffer. Writing to this register initiates an external microprocessor access to the static page of the section trace message buffer. When RWB is set high, a read access is initiated. The data read can be found in the SSTB Indirect Data register. When RWB is set low, a write access is initiated. The data in the SSTB Indirect Data register will be written to the addressed location in the static page.
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PMC-Sierra, Inc.
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Register 0x2B: SSTB Indirect Data Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default 0 0 0 0 0 0 0 0
This register contains the data read from the section trace message buffer after a read operation or the data to be written into the buffer before a write operation. D[7:0]: The indirect data bits (D[7:0]) reports the data read from a message buffer after an indirect read operation has completed. The data to be written to a buffer must be set up in this register before initiating an indirect write operation.
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PMC-Sierra, Inc.
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Register 0x30 (EXTD=0): RPOP Status/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R Type R/W Function Reserved Unused LOPV Unused PAISV PRDIV NEWPTRI NEWPTRE Default 0 X X X X X X 0
NOTE: To facilitate additional register mapping, shadow registers have been added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as the normal registers. The EXTD (extend register) bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers. This register allows the status of path level alarms to be monitored. NEWPTRE: The NEWPTRE bit is the interrupt enable for the receive new pointer status. When NEWPTRE is a logic one, an interrupt is generated when the pointer interpreter validates a new pointer. NEWPTRI: The NEWPTRI bit is the receive new pointer interrupt status bit. NEWPTRI is a logic one when the pointer interpreter has validated a new pointer value (H1, H2). NEWPTRI is cleared when this register is read. PRDIV: The PRDIV bit is read to determine the remote defect indication state. When PRDIV is a logic one, the S/UNI-622-POS has declared path RDI. PAISV: The PAISV bit is read to determine the path AIS state. When PAISV is a logic one, the S/UNI-622-POS has declared path AIS.
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PLOPV: The PLOPV bit is read to determine the loss of pointer state. When PLOPV is a logic one, the S/UNI-622-POS has declared LOP. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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PMC-Sierra, Inc.
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Register 0x30 (EXTD=1): RPOP Status/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R/W Type R/W R/W R/W R/W Function Reserved IINVCNT PSL5 Reserved Unused ERDIV[2] ERDIV[1] ERDIV[0] Default 0 0 0 0 X X X X
NOTE: To facilitate additional register mapping, shadow registers have been added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as the normal registers. The EXTD (extend register) bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers. The Status Register is provided at RPOP read address 0, if the extend register (EXTD) bit is set in register 6. ERDIV[2:0]: The ERDIV[2:0] bits reflect the current state of the detected enhanced RDI, (filtered G1 bits 5, 6, & 7). IINVCNT: When IINVCNT (Intuitive Invalid Pointer Counter) bit is set to 1, if the RPOP pointer interpreter state machine is in the LOP state, a new pointer received 3 consecutive times resets the inv_point count. If this bit is set to 0, the inv_point count will not be reset if pointer interpreter is in the LOP state and a new pointer received 3 consecutive times. PSL5: The PSL5 bit controls the filtering of the path signal label byte (C2). When PSL5 is set high, the PSL is updated when the same value is received for 5 consecutive frames. When the PSL5 is set low, the PSL is updated when the same value is received for 3 consecutive frames.
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Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x31 (EXTD=0): RPOP Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R Type R Function PSLI Unused LOPI Unused PAISI PRDII BIPEI FEBEI Default X X X X X X X X
NOTE: To facilitate additional register mapping, shadow registers have been added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as the normal registers. The EXTD (extend register) bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers. This register allows identification and acknowledgment of path level alarm and error event interrupts. FEBEI: The FEBEI bit is the path FEBE interrupt status bit. FEBEI is a logic one when a FEBE error is detected. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the path BIP-8 interrupt status bit. BIPEI is a logic one when a B3 error is detected. This bit is cleared when this register is read. PRDII: The PRDII bit is the path remote defect indication interrupt status bit. PRDII is a logic one when a change in the path RDI state or the auxiliary path RDI state occurs. This bit is cleared when this register is read.
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PAISI: The PAISI bit is the path alarm indication signal interrupt status bit. PAISI is a logic one when a change in the path AIS state occurs. This bit is cleared when this register is read. LOPI: The LOPI bit is the loss of pointer interrupt status bit. LOPI is a logic one when a change in the LOP state occurs. This bit is cleared when this register is read. PSLI: The PSLI bit is the change of path signal label interrupt status bit. PSLI is a logic one when a change is detected in the path signal label register. The current path signal label can be read from the RPOP Path Signal Label register. This bit is cleared when this register is read.
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Register 0x31 (EXTD=1): RPOP Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Type Function Unused Unused Unused Unused Unused Unused Unused ERDII Default X X X X X X X X
NOTE: To facilitate additional register mapping, shadow registers have been added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as the normal registers. The EXTD (extend register) bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers. This register allows identification and acknowledgment of path level alarm and error event interrupts. ERDII: The ERDII bit is set high when a change is detected in the received enhanced RDI state. This bit is cleared when the RPOP Interrupt Status register is read.
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Register 0x32: RPOP Pointer Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R Type R Function ILLJREQI Unused DISCOPAI INVNDFI ILLPTRI NSEI PSEI NDFI Default X X X X X X X X
This register allows identification and acknowledgment of pointer event interrupts. NDFI: The NDFI bit is set to logic one when the RPOP detects an active NDF event to a valid pointer value. NDFI is cleared when the RPOP Pointer Interrupt Status register is read. PSEI: The PSEI bit is set to logic one when the RPOP detects a positive stuff event. PSEI is cleared when the RPOP Pointer Interrupt Status register is read. NSEI: The NSEI bit is set to logic one when the RPOP detects a negative stuff event. NSEI is cleared when the RPOP Pointer Interrupt Status register is read. ILLPTRI: The ILLPTRI bit is set to logic one when the RPOP detects an illegal pointer event. ILLPTRI is cleared when the RPOP Pointer Interrupt Status register is read.
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INVNDFI: The INVNDFI bit is set to logic one when the RPOP detects an invalid NDF event. INVNDFI is cleared when the RPOP Pointer Interrupt Status register is read. DISCOPAI: The DISCOPAI bit is set to logic one when the RPOP detects a discontinuous change of pointer. DISCOPAI is cleared when the RPOP Pointer Interrupt Status register is read. ILLJREQI: The ILLJREQI bit is set to logic one when the RPOP detects an illegal pointer justification request event. ILLJREQI is cleared when the RPOP Pointer Interrupt Status register is read.
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Register 0x33 (EXTD=0): RPOP Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PSLE Reserved LOPE Reserved PAISE PRDIE BIPEE FEBEE Default 0 0 0 0 0 0 0 0
NOTE: To facilitate additional register mapping, shadow registers have been added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as the normal registers. The EXTD (extend register) bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers. This register allows interrupt generation to be enabled for path level alarm and error events. FEBEE: The FEBEE bit is the interrupt enable for path FEBEs. When FEBEE is a logic one, an interrupt is generated when a path FEBE is detected. BIPEE: The BIPEE bit is the interrupt enable for path BIP-8 errors. When BIPEE is a logic one, an interrupt is generated when a B3 error is detected. PRDIE: The PRDIE bit is the interrupt enable for path RDI. When PRDIE is a logic one, an interrupt is generated when the path RDI state changes. PAISE: The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic one, an interrupt is generated when the path AIS state changes.
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LOPE: The LOPE bit is the interrupt enable for LOP. When LOPE is a logic one, an interrupt is generated when the LOP state changes. PSLE: The PSLE bit is the interrupt enable for changes in the received path signal label. When PSLE is a logic one, an interrupt is generated when the received C2 byte changes. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x33 (EXTD=1): RPOP Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Type Function Unused Unused Unused Unused Unused Unused Unused ERDIE Default X X X X X X X 0
NOTE: To facilitate additional register mapping, shadow registers have been added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in the same way as the normal registers. The EXTD (extend register) bit must be set in register 0x36 to allow switching between accessing the normal registers and the shadow registers. This register allows interrupt generation to be enabled for path level alarm and error events. ERDIE: When REDIE is a logic one, an interrupt is generated when a path enhanced RDI is detected.
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Register 0x34: RPOP Pointer Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ILLJREQE Reserved DISCOPAE INVNDFE ILLPTRE NSEE PSEE NDFE Default 0 0 0 0 0 0 0 0
This register is used to enable pointer event interrupts. NDFE: When a logic one is written to the NDFE interrupt enable bit position, an interrupt is generated when a change in active offset due to the reception of an enabled NDF (NDF_enabled indication) occurs. PSEE: When a logic one is written to the PSEE interrupt enable bit position, an interrupt is generated when a positive pointer adjustment event is received. NSEE: When a logic one is written to the NSEE interrupt enable bit position, an interrupt is generated when a negative pointer adjustment is received. ILLPTRE: When a logic one is written to the ILLPTRE interrupt enable bit position, an interrupt is generated when an illegal pointer is received. INVNDFE: When a logic one is written to the INVNDFE interrupt enable bit position, an interrupt is generated when an invalid NDF code is received.
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DISCOPAE: When a logic one is written to the DISCOPAE interrupt enable bit position, an interrupt is generated when a change of pointer alignment event occurs. ILLJREQE: When a logic one is written to the ILLJREQE interrupt enable bit position, an interrupt is generated when an illegal pointer justification request is received. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x35: RPOP Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PTR[7] PTR[6] PTR[5] PTR[4] PTR[3] PTR[2] PTR[1] PTR[0] Default X X X X X X X X
Register 0x36: RPOP Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTR[9:0]: The PTR[7:0] bits contain the current pointer value as derived from the H1 and H2 bytes. To ensure reading a valid pointer, the NDFI, NSEI and PSEI bits of the RPOP Pointer Interrupt Status register should be read before and after reading this register to ensure that the pointer value did not changed during the register read. S0, S1: The S0 and S1 bits contain the two S bits received in the last H1 byte. These bits should be software debounced to ensure the proper values are received. R R R R Type R/W R/W R/W Function NDFPOR EXTD RDI10 Unused S1 S0 PTR[9] PTR[8] Default 0 0 0 X X X X X
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RDI10: The RDI10 bit controls the filtering of the remote defect indication and the auxiliary remote defect indication. When RDI10 is set to logic one, the PRDI and ARDI statuses are updated when the same value is received in the corresponding bit of the G1 byte for 10 consecutive frames. When PRDI10 is set to logic zero, the PRDI and ARDI statuses are updated when the same value is received for 5 consecutive frames. NDFPOR: The NDFPOR (new data flag pointer outside range) bit allows an NDF counter enable, if the pointer value is outside the range (0-782). If this bit is set high the definition for NDF counter enable is enabled NDF + ss. If this bit is set low the definition for NDF counter enable is enabled NDF + ss + offset in the range of 0 to 782. Note that this bit only allows the NDF counter to count towards LOP when the pointer is out of range and no active offset change will occur. EXTD: The EXTD bit extends the registers to facilitate additional mapping. If this bit is set high, the register mapping, for registers 0x30, 0x31 and 0x33, are extended.
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Register 0x37: RPOP Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PSL[7:0]: The PSL[7:0] bits contain the path signal label byte (C2). The value in this register is updated to a new path signal label value if the same new value is observed for three of five consecutive frames, depending on the status of the PSL5 bit. Type R R R R R R R R Function PSL[7] PSL[6] PSL[5] PSL[4] PSL[3] PSL[2] PSL[1] PSL[0] Default X X X X X X X X
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Register 0x38: RPOP Path BIP-8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PBE[7] PBE[6] PBE[5] PBE[4] PBE[3] PBE[2] PBE[1] PBE[0] Default X X X X X X X X
Register 0x39: RPOP Path BIP-8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PBE[15] PBE[14] PBE[13] PBE[12] PBE[11] PBE[10] PBE[9] PBE[8] Default X X X X X X X X
These registers allow path BIP-8 errors to be accumulated. PBE[15:0]: PBE[15:0] represent the number of B3 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register addresses. Such a write transfers the internally accumulated error count to the Path BIP-8 registers within a maximum of 7 s and simultaneously resets the internal counter to begin a
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new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-622-POS Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks.
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Register 0x3A: RPOP Path FEBE LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PFE[7] PFE[6] PFE[5] PFE[4] PFE[3] PFE[2] PFE[1] PFE[0] Default X X X X X X X X
Register 0x3B: RPOP Path FEBE MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PFE[15] PFE[14] PFE[13] PFE[12] PFE[11] PFE[10] PFE[9] PFE[8] Default X X X X X X X X
These registers allow path FEBEs to be accumulated. PFE[15:0]: Bits PFE[15:0] represent the number of path FEBE errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register addresses. Such a write transfers the internally accumulated error count to the Path FEBE Registers within approximately 7 s and simultaneously resets the internal
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counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-622-POS Master Reset and Identity register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP and TXFP blocks.
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Register 0x3C: RPOP RDI Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ARDIV: The auxiliary RDI bit (ARDIV) reports the current state of the path auxiliary RDI within the receive path overhead processor. ARDIE: When a logic one is written to the ARDIE interrupt enable bit position, an interrupt is generated when a change in the path auxiliary RDI state occurs. BLKFEBE: When set high, the block FEBE bit (BLKFEBE) causes path FEBE errors to be reported and accumulated on a block basis. A single path FEBE error is accumulated for a block if the received FEBE code for that block is between 1 and 8 inclusive. When BLKFEBE is set low, path FEBE errors are accumulated on a error basis. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R R/W R/W Type Function Unused Unused Reserved BLKFEBE Unused Reserved ARDIE ARDIV Default X X 0 0 X 0 0 X
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Register 0x3D: RPOP Ring Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BLKBIPO: When set high, the block BIP-8 output bit (BLKBIPO) indicates that path BIP8 errors are to be reported on a block basis to the transmit path overhead processor (TPOP) block. A single path BIP error is reported to the return transmit path overhead processor if any of the path BIP-8 results indicates a mismatch. When BLKBIP is set low, BIP-8 errors are reported on a bit basis. BLKBIP: When set high, the block BIP-8 bit (BLKBIP) indicates that path BIP-8 errors are to be accumulated on a block basis. A single BIP error is accumulated if any of the BIP-8 results indicates a mismatch. When BLKBIP is set low, BIP8 errors are accumulated on a bit basis. ENSS: The enable size bit (ENSS) controls whether the SS bits in the payload pointer are used to determine offset changes in the pointer interpreter state machine. When a logic one is written to this bit, an incorrect SS bit pattern (i.e., not equal to 10) will prevent RPOP from issuing NDF_enable, inc_ind, new_point and dec_ind indications. When a logic zero is written to this bit, the received SS bits do not affect active offset change events. SOS: The stuff opportunity spacing control bit (SOS) controls the spacing between consecutive pointer justification events on the receive stream. When a logic one is written to this bit, the definition of inc_ind and dec_ind indications Type R/W R/W R/W R/W R/W R/W R/W R/W Function SOS ENSS BLKBIP Reserved BLKBIPO Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0
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includes the requirement that active offset changes have occurred a least three frame ago. When a logic zero is written to this bit, pointer justification indications in the receive stream are followed without regard to the proximity of previous active offset changes. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x40: TPOP Control/Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAIS: The PAIS bit controls the insertion of STS path alarm indication signal. When a logic one is written to this bit position, the complete SPE, and the pointer bytes (H1, H2, and H3) are overwritten with the all-ones pattern. When a logic zero is written to this bit position, the pointer bytes and the SPE are processed normally.DBIP8: The DBIP8 bit controls the insertion of bit errors continuously in the B3 byte. When DBIP8 is a logic one, the B3 byte is inverted. PERSIST The path far end receive failure alarm persistence bit (PERSIST) controls the persistence of the RDI asserted into the transmit stream. When PERSIST is a logic one, the RDI code inserted into the transmit stream as a result of consequential actions is asserted for a minimum of 20 frames in nonenhanced RDI mode, or the last valid RDI code before an idle code (idle codes are when bits 5,6,7 are 000, 001, or 011) is asserted for 20 frames in enhanced RDI mode. When PERSIST is logic zero, the transmit RDI code changes immediately based on received alarm conditions. EPRDISRC The enhanced path receive defect indication alarm source bit (EPRDISRC) controls the source of RDI input to be inserted onto the G1 byte. When EPRDIEN is logic zero, the extended RDI bits of the G1 byte not overwritten by the TPOP block, regardless of EPRDISRC. When EPRDIEN is logic one and EPRDISCR is logic zero, the extended RDI bits of the G1 byte, bits 6 and R/W R/W R/W R/W R/W R/W R/W Type Function Unused EPRDIEN EPRDISRC PERSIST Reserved Reserved DBIP8 PAIS Default X 0 0 0 0 0 0 0
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7, are inserted according to the value in the G1[1:0] register bits (register 0x49). When EPRDIEN is logic one and EPRDISCR is logic one, the value register 0x49 G1[1:0] is ignored and the EPRDI bits in the G1 byte are set according to the setting of the Channel Auto Enhanced Path RDI Control registers (0x92 and 0x93). EPRDIEN The enhanced path receive defect indication alarm enable bit (EPRDIEN) controls the use of 3-bit RDI mode. When EPRDIEN is set to logic zero, the basic path RDI scheme is used and only G1[5] is used to indicate PRDI. When EPRDIEN is set to logic one, the enhanced path RDI scheme is used and the three G1[7:5] bits are used to indicate PRDI. The actual three bit code will be controlled according to the EPRDISRC. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x41: TPOP Pointer Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved FTPTR SOS PLD NDF NSE PSE Reserved Default 0 0 0 0 0 0 0 0
This register allows control over the transmitted payload pointer for diagnostic purposes. PSE: The PSE bit controls the insertion of positive pointer movements. A zero to one transition on this bit enables the insertion of a single positive pointer justification in the outgoing stream. This register bit is automatically cleared when the pointer movement is inserted. NSE: The NSE bit controls the insertion of negative pointer movements. A zero to one transition on this bit enables the insertion of a single negative pointer justification in the outgoing stream. This register bit is automatically cleared when the pointer movement is inserted. NDF: The NDF bit controls the insertion of new data flags in the inserted payload pointer. When a logic one is written to this bit position, the pattern contained in the NDF[3:0] bit positions in the TPOP Arbitrary Pointer MSB Register is inserted continuously in the payload pointer. When a logic zero is written to this bit position, the normal pattern (0110) is inserted in the payload pointer. PLD: The PLD bit controls the loading of the pointer value contained in the TPOP Arbitrary Pointer Registers. Normally the TPOP Arbitrary Pointer Registers
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are written to set up the arbitrary new pointer value, the S-bit values, and the NDF pattern. A logic one is then written to this bit position to load the new pointer value. The new data flag bit positions are set to the programmed NDF pattern for the first frame; subsequent frames have the new data flag bit positions set to the normal pattern (0110) unless the NDF bit described above is set to a logic one. Note: When loading an out of range pointer (that is a pointer with a value greater than 782), the TPOP continues to operate with timing based on the last valid pointer value. The out of range pointer value will of course be inserted in the STS-12c/STM-4-4c stream. Although a valid SPE will continue to be generated, it is unlikely to be extracted by downstream circuitry, which should be in a loss of pointer state. This bit is automatically cleared after the new payload pointer has been loaded. SOS: The SOS bit controls the stuff opportunity spacing between consecutive SPE positive or negative stuff events. When SOS is a logic zero, stuff events may be generated every frame as controlled by the PSE and NSE register bits described above. When SOS is a logic one, stuff events may be generated at a maximum rate of once every four frames. FTPTR: The force transmit pointer bit (FTPTR) enables the insertion of the pointer value contained in the Arbitrary Pointer Registers into the POUT[7:0] stream for diagnostic purposes. This allows the ATM/POS payload mapping circuitry to continue functioning normally and a valid SPE to continue to be generated, although it is unlikely to be extracted by downstream circuitry as the downstream pointer processor should be in a loss of pointer state. If FTPTR is set to logic one, the APTR[9:0] bits of the Arbitrary Pointer Registers are inserted into the H1 and H2 bytes of the transmit stream. At least one corrupted pointer is guaranteed to be sent. If FTPTR is a logic zero, a valid pointer is inserted. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x43: TPOP Current Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function CPTR[7] CPTR[6] CPTR[5] CPTR[4] CPTR[3] CPTR[2] CPTR[1] CPTR[0] Default X X X X X X X X
Register 0x44: TPOP Current Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTR[9:0]: The CPTR[9:0] bits reflect the value of the current payload pointer being inserted in the outgoing stream. The value may be changed by loading a new pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers, or by inserting positive and negative pointer movements using the PSE and NSE register bits. It is recommended the CPTR[9:0] value be software debounced to ensure a correct value is received. R R Type Function Unused Unused Unused Unused Unused Unused CPTR[9] CPTR[8] Default X X X X X X X X
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Register 0x45: TPOP Arbitrary Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function APTR[7] APTR[6] APTR[5] APTR[4] APTR[3] APTR[2] APTR[1] APTR[0] Default 0 0 0 0 0 0 0 0
This register allows an arbitrary pointer to be inserted for diagnostic purposes. APTR[7:0]: The APTR[7:0] bits, along with the APTR[9:8] bits in the TPOP Arbitrary Pointer MSB Register are used to set an arbitrary payload pointer value. The arbitrary pointer value is inserted in the outgoing stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register. If the FTPTR bit in the TPOP Pointer Control register is a logic one, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the transmit stream.
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Register 0x46: TPOP Arbitrary Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function NDF[3] NDF[2] NDF[1] NDF[0] S[1] S[0] APTR[9] APTR[8] Default 1 0 0 1 1 0 0 0
This register allows an arbitrary pointer to be inserted for diagnostic purposes. APTR[9:8]: The APTR[9:8] bits, along with the APTR[7:0] bits in the TPOP Arbitrary Pointer LSB Register are used to set an arbitrary payload pointer value. The arbitrary pointer value is inserted in the outgoing stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register. If the FTPTR bit in the TPOP Pointer Control register is a logic one, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the transmit stream. S[1:0]: The S[1:0] bits contain the value inserted in the S[1:0] bit positions (also referred to as the unused bits) in the payload pointer. These bits are continuously inserted into the transmit stream. NDF[3:0]: The NDF[3:0] bits contain the value inserted in the NDF bit positions when an arbitrary new payload pointer value is inserted (using the PLD bit in the TPOP Pointer Control Register) or when new data flag generation is enabled using the NDF bit in the TPOP Pointer Control Register.
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Register 0x47: TPOP Path Trace Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function J1[7] J1[6] J1[5] J1[4] J1[3] J1[2] J1[1] J1[0] Default 0 0 0 0 0 0 0 0
This register allows control over the path trace byte. J1[7:0]: The J1[7:0] bits are inserted in the J1 byte position in the transmit stream .
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Register 0x48: TPOP Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function C2[7] C2[6] C2[5] C2[4] C2[3] C2[2] C2[1] C2[0] Default 0 0 0 0 0 0 0 1
This register allows control over the path signal label. Upon reset the register defaults to 0x01, which signifies an equipped unspecific payload. C2[7:0]: The C2[7:0] bits are inserted in the C2 byte position in the transmit stream. C2 should be reprogrammed with the value 0x13 when transmitting ATM payload data. C2 should be reprogrammed with the value 0x16 when transmitting scrambled packet over SONET payload data. C2 may be reprogrammed with the value 0xCF when transmitting unscrambled packet over SONET payload data. However, POS scrambling in the TXFP block must be turned off.
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Register 0x49: TPOP Path Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function FEBE[3] FEBE[2] FEBE[1] FEBE[0] PRDI APRDI G1[1] G1[0] Default 0 0 0 0 0 0 0 0
This register allows control over the path status byte. G1[1:0]: The G1[1:0] bits are inserted in bits 1 and 2 of the Path Status Byte G1. These bits are ignored when EPRDIEN is logic zero or when EPRDIEN and EPRDISRC are both logic one. See the description of EPRDIEN and EPRDISRC for more details on how G1 can be controlled. APRDI: The APRDI bit controls the insertion of the auxiliary path remote defect indication. When APRDI is a logic one, the APRDI bit position in the path status byte is set high. When APRDI is a logic zero, the APRDI bit position in the path status byte is set low. PRDI: The PRDI bit controls the insertion of the path remote defect indication. When a logic one is written to this bit position, the PRDI bit position in the path status byte is set high. When a logic zero is written to this bit position, the PRDI bit position in the path status byte is set low. This bit is ignored when EPRDIEN is logic zero or when EPRDIEN and EPRDISRC are both logic one. FEBE[3:0]: The FEBE[3:0] bits are inserted in the FEBE bit positions in the path status byte. The value contained in FEBE[3:0] is cleared after being inserted in the
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path status byte. Any non-zero FEBE[3:0] value overwrites the value that would normally have been inserted based on the number of FEBEs accumulated on primary input FEBE during the last frame. When reading this register, a non-zero value in these bit positions indicates that the insertion of this value is still pending.
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Register 0x4E: TPOP Concatenation LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function CONCAT[7] CONCAT[6] CONCAT[5] CONCAT[4] CONCAT[3] CONCAT[2] CONCAT[1] CONCAT[0] Default 1 1 1 1 1 1 1 1
Register 0x4F: TPOP Concatenation MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function CONCAT[15] CONCAT[14] CONCAT[13] CONCAT[12] CONCAT[11] CONCAT[10] CONCAT[9] CONCAT[8] Default 1 0 0 1 0 0 1 1
These registers allow control over the concatenation indication values transmitted in SONET/SDH pointers. CONCAT[15:0]: The CONCAT[15:0] bits control the value inserted in the some of the H1 and H2 byte positions when transmitting an STS-12c or STM-4-4c stream. The value written to CONCAT[15:8] is inserted in the H1 byte position of STS-1 #5 and STS-1 #9 in the concatenated stream. The value written to CONCAT[7:0] is inserted in the H2 byte position of STS-1 #5 and STS-1 #9 in the concatenated stream. The default values represent the normal concatenation
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indication (all ones in the pointer bits, zeros in the unused bits, and NDF indication).
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Register 0x50: SPTB Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ZEROEN RRAMACC RTIUIE RTIMIE PER5 TNULL NOSYNC LEN16 Default 0 0 0 0 0 1 0 0
This register controls the receive and transmit portions of the SPTB. LEN16: The LEN16 bit selects the length of the path trace message to be 16 bytes or 64 bytes. When LEN16 is a logic one, a 16 byte path trace message is selected. When LEN16 is a logic zero, a 64 byte path trace message is selected. NOSYNC: The NOSYNC bit disables the writing of the path trace message into the trace buffer to be synchronized to the content of the message. When LEN16 is a logic one and NOSYNC is a logic zero, the receive path trace message byte with its most significant bit set will be written to the first location in the buffer. When LEN16 and NOSYNC are logic zero, the byte after the carriage return/linefeed (CR/LF) sequence will be written to the first location in the buffer. When NOSYNC is a logic one, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. TNULL: The TNULL bit controls the insertion of an all-zero path trace identifier message in the transmit stream. When TNULL is a logic one, the contents of the transmit buffer is ignored and all-zeros bytes are inserted. When TNULL is a logic zero, the contents of the transmit path trace buffer is sent to TPOP for insertion into the J1 transmit path overhead byte. TNULL should be set high before changing the contents of the trace buffer to avoid sending partial messages.
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PER5: The PER5 bit controls the number of times a path trace identifier message must be received unchanged before being accepted. When PER5 is a logic one, a message is accepted when it is received unchanged five times consecutively. When PER5 is a logic zero, the message is accepted after three identical repetitions. RTIMIE: The RTIMIE bit controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state. When RTIMIE is a logic one, changes in match state activates the interrupt output. RTIUIE: The RTIUIE bit controls the activation of the interrupt output when the receive identifier message changes state. When RTIUIE is a logic one, changes in the received path trace identifier message stable/unstable state will activate the interrupt output. RRAMACC: The RRAMACC bit directs read and writes access to either the receive or transmit path trace buffer. When RRAMACC is a logic one, microprocessor accesses are directed to the receive path trace buffer. When RRAMACC is a logic zero, microprocessor accesses are directed to the transmit path trace buffer. ZEROEN: The zero enable bit (ZEROEN) enables TIM assertion and removal based on an all ZERO's path trace message string. When ZEROEN is set high, all ZERO's path trace message strings are considered when entering and exiting TIM states. When ZEROEN is set low, all ZERO's path trace message strings are ignored. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x51: SPTB Path Trace Identifier Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R Function BUSY Unused Unused Unused RTIUI RTIUV RTIMI RTIMV Default 0 X X X X X X X
This register reports the path trace identifier status of the SPTB. RTIMV: The RTIMV bit reports the match/mismatch status of the identifier message framer. RTIMV is a logic one when the accepted identifier message differs from the expected message written by the microprocessor. RTIMV is a logic zero when the accepted message matches the expected message. RTIMI: The RTIMI bit is a logic one when match/mismatch status of the trace identifier framer changes state. This bit is cleared when this register is read. RTIUV: The RTIUV bit reports the stable/unstable status of the identifier message framer. RTIUV is a logic one when the current received path trace identifier message has not matched the previous message for eight consecutive messages. RTIUV is a logic zero when the current message becomes the accepted message as determined by the PER5 bit in the SPTB Control register. RTIUI: The RTIUI bit is a logic one when stable/unstable status of the trace identifier framer changes state. This bit is cleared when this register is read.
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BUSY: The BUSY bit reports whether a previously initiated indirect read or write to a message buffer has been completed. BUSY is set to a logic one immediately upon writing to the SPTB Indirect Address register, and stays high until the initiated access is completed. This register should be polled to determine when new data is available in the SPTB Indirect Data register.
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Register 0x52: SPTB Indirect Address Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0] Default 0 0 0 0 0 0 0 0
This register supplies the address used to index into path trace identifier buffers. A[6:0]: The indirect read address bits (A[6:0]) are used to address the path trace identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference the captured message page while addresses 64 to 127 reference the expected message page of the receive path trace buffer. The captured message page contains the identifier bytes extracted from the receive stream. The expected message page contains the path trace message to which the captured message page is compared. When RRAMACC is set low, addresses 0 to 63 reference the transmit path trace buffer which contains the path trace message inserted in the transmit stream. RWB: The access control bit (RWB) selects between an indirect read or write access to the selected path trace buffer (receive or transmit as determined by the RRAMACC bit). Writing to this register initiates an access to the selected path trace buffer. When RWB is a logic one, a read access is initiated. The addressed location's contents are placed in the SPTB Indirect Data register. When RWB is a logic zero, a write access is initiated. The data in the SPTB Indirect Data register is written to the addressed location in the selected buffer.
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Register 0x53: SPTB Indirect Data Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default 0 0 0 0 0 0 0 0
This register contains the data read from the path trace message buffer after a read operation or the data to be written into the buffer before a write operation. D[7:0]: The indirect data bits (D[7:0]) contain the data read from either the transmit or receive path trace buffer after an indirect read operation is completed. The data that is written to a buffer is set up in this register before initiating the indirect write operation.
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Register 0x54: SPTB Expected Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EPSL[7:0]: The EPSL[7:0] bits contain the expected path signal label byte (C2). EPSL[7:0] is compared with the C2 byte extracted from the receive stream. A path signal label match or mismatch is declared based upon the following table: Expect 00 00 00 01 01 01 XX XX XX XX Receive 00 01 XX 00 01 XX 00 01 XX YY Action Declared Match Mismatch Mismatch Mismatch Match Match Mismatch Match Match Mismatch Type R/W R/W R/W R/W R/W R/W R/W R/W Function EPSL[7] EPSL[6] EPSL[5] EPSL[4] EPSL[3] EPSL[2] EPSL[1] EPSL[0] Default 0 0 0 0 0 0 0 0
EPSL[7:0] should be reprogrammed with the value 0x13 when receiving ATM payload data. EPSL[7:0] should be reprogrammed with the value 0x16 when receiving scrambled packet over SONET payload data.
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Register 0x55: SPTB Path Signal Label Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPSLMV: The RPSLMV bit reports the match/mismatch status between the expected and the accepted path signal label. RPSLMV is a logic one when the accepted PSL results in a mismatch with the expected PSL written by the microprocessor. RPSLMV is a logic zero when the accepted PSL results in a match with the expected PSL. RPSLMI: The RPSLMI bit is a logic one when the match/mismatch status between the accepted and the expected path signal label changes state. This bit is cleared when this register is read. RPSLUV: The RPSLUV reports the stable/unstable status of the path signal label in the receive stream. RPSLUV is a logic one when the current received C2 byte differs from the previous C2 byte for five consecutive frames. RPSLUV is a logic zero when the same PSL code is received for five consecutive frames. RPSLUI: The RPSLUI bit is a logic one when the stable/unstable status of the path signal label changes state. This bit is cleared when this register is read. R R R R Type R/W R/W Function RPSLUIE RPSLMIE Unused Unused RPSLUI RPSLUV RPSLMI RPSLMV Default 0 0 X X X X X X
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RPSLMIE: The RPSLMIE bit is the interrupt enable for the path signal label match/mismatch status. When RPSLMIE is a logic one, changes in the match state generate an interrupt. RPSLUIE: The RPSLUIE bit is the interrupt enable for the path signal label stable/unstable status. When RPSLUIE is a logic one, changes in the stable/unstable state generate an interrupt.
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Register 0x58: CSPI Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROOLI: The ROOLI bit is the reference out of lock interrupt status bit. ROOLI is set high when the ROOLV register goes high, indicating that the PLL is not locked to the reference clock REFCLK. ROOLI is cleared when this register is read. R R/W R/W Type Function Unused Unused Reserved Reserved Unused Unused Unused ROOLI Default X X 0 0 X X X X
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Register 0x59: CSPI Status and Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROOLE: The ROOLE bit enables the reference out of lock indication interrupt. When ROOLE is set high, an interrupt is generated upon assertion and negation events of the ROOLV register. When ROOLE is set low, changes in the ROOL status do not generate an interrupt. ROOLV: The transmit reference out of lock status indicates the clock synthesis phase lock loop is unable to lock to the reference clock on REFCLK. ROOLV is a logic one if the divided down synthesized clock frequency is not within approximately 488ppm of the REFCLK frequency. At startup, ROOLV may remain high for several hundred millisecond while the PLL obtains lock. When the AVD power supply of the S/UNI-622-POS is subjected to a change greater than the 5% tolerance specified for the 3.3V analog supply pins, the Clock Synthesis Unit may lose lock to the reference. When this occurs, the ROOLV will remain high until the CSU is reset using the CSURESETLPF and CSURSET registers. R/W R Type Function Unused Unused Unused ROOLV Unused Unused Unused ROOLE Default X X X X X X X 0
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Register 0x5A: CSPI Clock Synthesis Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type R/W R/W R/W R/W Function Reserved CSURESET CSURESETLPF Reserved Unused Reserved Reserved Reserved Default 0 0 0 0 X 0 0 0
The CSU Control register provides direct access to the CSU. When the CSU does not lock properly (ROOLV remains high), the CSU may be re-initialized using this register. When the AVD power supply of the S/UNI-622-POS is subjected to a change greater than the 5% tolerance specified for the 3.3V analog supply pins, the Clock Synthesis Unit may lose lock to the reference clock. When this occurs, the ROOLV will remain high until the CSU is reset using the CSURESETLPF and CSURSET registers. The S/UNI-622-POS will operate normally if the power supply does not vary beyond the specified 5% tolerance.
CSURESETLPF: The CSU low pass filter (LPF) reset control CSURESETLPF bit provides a software reset for the CSU-622 ABC. When CSURESETLPF is set high, the CSU RESETLPF input is set high forcing the CSU LPF into reset. When CSURESETLPF is set low, the CSU RESETLPF input is controlled by the system reset. The CSURESETLPF and CSURESET should be held high for 10ms to properly reset the CSU.
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CSURESET: The CSU reset control CSURESET bit provides a software reset for the CSU622 ABC. When CSURESET is set high, the CSU RESET input is set high forcing the CSU into reset. When CSURESET is set low, the CSU RESET input is controlled by the system reset and digital test mode. The CSURESETLPF and CSURESET should be held high for 10ms to properly reset the CSU.
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Register 0x5C: CRSI Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DOOLI: The DOOLI bit is the data out of lock interrupt status bit. DOOLI is set high when the DOOLV bit goes high, indicating the CRU has gone out of lock. DOOLI is cleared when this register is read. ROOLI: The ROOLI bit is the reference out of lock interrupt status bit. ROOLI is set high when the ROOLV register changes state, indicating that either the PLL is locked to the reference clock REFCLK or is in out of lock. ROOLI is cleared when this register is read. LOTI: The LOTI bit is the loss of transition interrupt status bit. LOTI is set high when a loss of transition event occurs. A loss of transition is defined as either the SD input set low or more than 96 consecutive ones or zeros received. LOTI is cleared when this register is read. R R R Type R/W R/W R/W R/W Function SDINV PFPEN SENB Reserved Unused LOTI ROOLI DOOLI Default 0 0 0 0 X X X X
SENB: The loss of signal transition detector enable (SENB) bit enables the declaration of loss of transition (LOT) when more than 96 consecutive ones or zeros occurs in the receive data. When SENB is a logic zero, a loss of transition is declared when more than 96 consecutive ones or zeros occurs in the receive data or when the SD input is low. When SENB is a logic one, a loss of transition is declared only when the SD input is low.
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PFPEN: The parallel frame pulse enable (PFPEN) enables the parallel frame pulse operation when the parallel data interface is enabled (LIFSEL is set high). When PFPEN is a logic zero, the FPIN input is ignored and the SONET/SDH framing is performed on the PIN[7:0] data. When PFPEN is logic one, the SONET/SDH framer is ignored and the PIN[7:0] bus is assumed to be byte aligned marked with the FPIN frame pulse. PFPEN is ignored when the LIFSEL input is set low. SDINV: The signal detect input invert (SDINV) controls the polarity of the SD input. The value of the SD input is logically XOR'ed with the value of the SDINV register. Therefore, when SDINV is a logic zero, valid signal power is indicated by the SD input high. When SDINV is a logic one, valid signal power is indicated by the SD input low.
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Register 0x5D: CRSI Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DOOLE: The DOOLE bit is an interrupt enable for the recovered data out of lock status. When DOOLE is set to logic one, an interrupt is generated upon assertion events of the DOOLV register. When ROOLE is set low, changes in the DOOL status do not generate an interrupt. ROOLE: The ROOLE bit enables the reference out of lock indication interrupt. When ROOLE is set high, an interrupt is generated upon assertion and negation events of the ROOLV register. When ROOLE is set low, changes in the ROOL status do not generate an interrupt. LOTE: The LOTE bit enables the loss of transition indication interrupt. When LOTE is set high, an interrupt is generated upon assertion events of the LOTV register. When LOTE is set low, changes in the LOTV status do not generate an interrupt. DOOLV: The recovered data out of lock status indicates the clock recovery phase locked loop is unable to recover and lock to the input data stream. DOOLV is a logic one if the divided down recovered clock frequency is not within approximately 488ppm of the REFCLK frequency or if no transitions have occurred on the RXD input for more than 96 bits. R/W R/W R/W Type R R R R Function LOCK LOTV ROOLV DOOLV Unused LOTE ROOLE DOOLE Default X X X X X 0 0 0
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ROOLV: The recovered reference out of lock status indicates the clock recovery phase locked loop is unable to lock to the reference clock on REFCLK. ROOLV is a logic one if the divided down synthesized clock frequency is not within approximately 488ppm of the REFCLK frequency. At startup, ROOLV may remain high for several hundred millisecond while the PLL obtains lock. LOTV: The loss of transition status indicates the receive power is lost or at least 97 consecutive ones or zeros have been received. LOTV is a logic zero if the SD input is high or fewer than 97 consecutive ones or zeros have been received. LOTV is a logic one if the SD input is low or more than 96 consecutive ones or zeros have been received. LOCK: The CRU reference locking status indicates if the CRU is locking to the reference clock or is locking to the receive data. LOCK is a logic zero if the CRU is locking or locked to the reference clock. LOCK is a logic one if the CRU is locking or locked to the receive data. LOCK is invalid if the CRU is not used.
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Register 0x5E: CRSI Clock Recovery Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTYPE: The CRU recovery mode register sets the PLL recovery mode for jitter transfer and jitter tolerance. When RTYPE is a logic zero, the CRU operates in LAN mode with improved tolerance and relaxed jitter transfer. When RTYPE is a logic one, the CRU operates in WAN mode with compliant jitter transfer. For proper operation, leave pins C0 and C1 floating when RTYPE is logic zero. When RTYPE is logic one, the specified capacitor must be connected between C0 and C1 for proper operation. R/W R/W Type R/W R/W R/W R/W Function Reserved Reserved RTYPE Reserved Unused Unused Reserved Reserved Default 0 0 0 0 X X 0 0
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Register 0x60: RXCP Configuration 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DISCOR: The DISCOR bit controls the HCS error correction algorithm. When DISCOR is a logic zero, the error correction algorithm is enabled, and single-bit errors detected in the cell header are corrected. When DISCOR is a logic one, the error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable HCS error. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to comparison. When HCSADD is a logic one, the polynomial is added, and the resulting HCS is compared. When HCSADD is a logic zero, the polynomial is not added, and the unmodified HCS is compared. HDSCR: HDSCR enables the self-synchronous x43 + 1 descrambler to continue running through the bytes which should contain the ATM cell headers. When HSCR is set low, the descrambling polynomial will function only over the ATM payload bytes. When HDSCR is set high, the descrambling polynomial will function over all bytes, including the 5 ATM header bytes. This function is available for use with PPP packets and flags which are scrambled at the source to prevent the generation of "killer" sequences. R/W R/W R/W Type R/W R/W Function DDSCR HDSCR Unused Unused Unused HCSADD Reserved DISCOR Default 0 0 X X X 1 0 0
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DDSCR: The DDSCR bit controls the descrambling of the cell payload with the polynomial x43 + 1. When DDSCR is set high, cell payload descrambling is disabled. When DDSCR is set low, payload descrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x61: RXCP Configuration 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function CCDIS HCSPASS IDLEPASS Reserved Reserved Reserved HCSFTR[1] HCSFTR[0] Default 0 0 0 0 0 0 0 0
HCSFTR[1:0]: The HCS filter bits, HCSFTR[1:0] indicate the number of consecutive errorfree cells required, while in detection mode, before reverting back to correction mode. HCSFTR[1:0] 00 01 10 11 Cell Acceptance Threshold One ATM cell with correct HCS before resumption of cell acceptance. This cell is accepted. Two ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted. Four ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted. Eight ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted.
IDLEPASS: The IDLEPASS bit controls the function of the Idle Cell filter. When IDLEPASS is written with a logic zero, all cells that match the Idle Cell Header Pattern and Idle Cell Header Mask are filtered out. When IDLEPASS is a logic one, the Idle Cell Header Pattern and Mask registers are ignored. The default state of this bit and the bits in the Idle Cell Header Mask and Idle Cell Header Pattern Registers enable the dropping of idle cells.
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HCSPASS: The HCSPASS bit controls the dropping of cells based on the detection of an uncorrectable HCS error. When HCSPASS is a logic zero, cells containing an uncorrectable HCS error are dropped. When HCSPASS is a logic one, cells are passed to the receive FIFO regardless of errors detected in the HCS. Additionally, the HCS verification finite state machine never exits the correction mode. Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states unless the CCDIS bit in this register is set high. CCDIS: The CCDIS bit can be used to disable all cell filtering and cell delineation. All payload data read from the RXCP is passed into its FIFO without the requirement of having to find cell delineation first. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x62: RXCP FIFO/UTOPIA Control and Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST is set low, the FIFO operates normally. When FIFORST is set high, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST. Activating this bit during a cell transfer may result in a truncated cell on the System Interface. RCALEVEL0: The RCA level 0 bit, RCALEVEL0, determines when the RCA transitions low for Level 2 operation. When RCALEVEL0 is set high, a high-to-low transition on output RCA indicates that the receive FIFO is empty and RCA will deassert on the rising RFCLK edge after word 27 (of the 27 word cell structure) is output. When RCALEVEL0 is set low, a high-to-low transition on output RCA indicates that the receive FIFO is near empty and RCA will de-assert on the rising RFCLK edge after word 13 (of the 27 word cell structure) is output. RCALEVEL0 must be set high when the system interface is configured for Level 3 operation. RCAINV: The RCAINV bit inverts the polarity of the RCA output signal for Level 2 operation. When RCAINV is a logic one, the polarity of RCA is inverted (RCA at logic zero means there is a receive cell available to be read). When RCAINV is a logic zero, the polarity of RCA is not inverted. R/W R/W R/W Type R/W Function RXPTYP Unused RCAINV RCALEVEL0 Unused Unused Unused FIFORST Default 0 X 0 1 X X X 0
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RCAINV must be set low when the system interface is configured for Level 3 operation. RXPTYP: The RXPTYP bit selects even or odd parity for output RPRTY for Level 2 operation. When set high, output RPRTY is the even parity bit for outputs RDAT[15:0]. When RXPTYP is set low, RPRTY is the odd parity bit for outputs RDAT[15:0]. RXPTYP must be set low when the system interface is configured for Level 3 operation.
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Register 0x63: RXCP Interrupt Enable and Counter Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDE: The LCDE bit enables the generation of an interrupt due to a change in the LCD state. When LCDE is set high, the interrupt is enabled. FOVRE: The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition. When FOVRE is set high, the interrupt is enabled. HCSE: The HCSE bit enables the generation of an interrupt due to the detection of a corrected or an uncorrected HCS error. When HCSE is set high, the interrupt is enabled. OOCDE: The OOCDE bit enables the generation of an interrupt due to a change in cell delineation state. When OOCDE is set high, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the RXCP Count registers. When XFERE is set high, the interrupt is enabled. OVR: The OVR bit is the overrun status of the RXCP Performance Monitoring Count registers. A logic one in this bit position indicates that a previous transfer R/W R/W R/W R/W R/W Type R R Function XFERI OVR Unused XFERE OOCDE HCSE FOVRE LCDE Default X X X 0 0 0 0 0
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(indicated by XFERI being logic one) has not been acknowledged before the next accumulation interval has occurred and that the contents of the RXCP Count registers have been overwritten. OVR is set low when this register is read. XFERI: The XFERI bit indicates that a transfer of RXCP Performance Monitoring Count data has occurred. A logic one in this bit position indicates that the RXCP Count registers have been updated. This update is initiated by writing to one of the RXCP Count register locations or to the S/UNI-622-POS, Master Reset and Identity register. XFERI is set low when this register is read.
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Register 0x64: RXCP Status/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDI: The LCDI bit is set high when there is a change in the loss of cell delineation (LCD) state. This bit is reset immediately after a read to this register. FOVRI: The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already full. This bit is reset immediately after a read to this register. Continuous over-writing of the FIFO results in only one interrupt. UHCSI: The UHCSI bit is set high when an uncorrected HCS error is detected. This bit is reset immediately after a read to this register. CHCSI: The CHCSI bit is set high when a corrected HCS error is detected. This bit is reset immediately after a read to this register. OOCDI: The OOCDI bit is set high when the RXCP enters or exits the SYNC state. The OOCDV bit indicates whether the RXCP is in the SYNC state or not. The OOCDI bit is reset immediately after a read to this register. LCDV: The LCDV bit gives the Loss of Cell Delineation state. When LCD is high, an out of cell delineation (OCD) defect has persisted for the number of cells R R R R R Type R R Function OOCDV LCDV Unused OOCDI CHCSI UHCSI FOVRI LCDI Default X X X X X X X X
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specified in the LCD Count Threshold register. When LCD is low, no OCD has persisted for the number of cells specified in the LCD Count Threshold register. The cell time period can be varied by using the LCDC[7:0] register bits in the RXCP LCD Count Threshold register. OOCDV: The OOCDV bit indicates the cell delineation state. When OOCDV is high, the cell delineation state machine is in the 'HUNT' or 'PRESYNC' state and is hunting for the cell boundaries. When OOCDV is low, the cell delineation state machine is in the 'SYNC' state and cells are passed through the receive FIFO.
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Register 0x65: RXCP LCD Count Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused Unused Unused LCDC[10] LCDC[9] LCDC[8] Default X X X X X 0 0 1
Register 0x66: RXCP LCD Count Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDC[10:0]: The LCDC[10:0] bits represent the number of consecutive cell periods the receive cell processor must be out of cell delineation before loss of cell delineation (LCD) is declared. Likewise, LCD is not de-asserted until receive cell processor is in cell delineation for the number of cell periods specified by LCDC[10:0]. The default value of LCD[10:0] is 360, which translates to an average cell period of 0.71 s and a default LCD integration period of 255 s. Type R/W R/W R/W R/W R/W R/W R/W R/W Function LCDC[7] LCDC[6] LCDC[5] LCDC[4] LCDC[3] LCDC[2] LCDC[1] LCDC[0] Default 0 1 1 0 1 0 0 0
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Register 0x67: RXCP Idle Cell Header Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GFC[3:0]: The GFC[3:0] bits contain the pattern to match in the first, second, third, and fourth bits of the first octet of the 53-octet cell, in conjunction with the Idle Cell Header Mask Register. The IDLEPASS bit in the RXCP Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern. Note that an all-zeros pattern must be present in the VPI and VCI fields of the idle or unassigned cell. PTI[2:0]: The PTI[2:0] bits contain the pattern to match in the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell, in conjunction with the Idle Cell Header Mask Register. The IDLEPASS bit in the RXCP Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern. CLP: The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53-octet cell, in conjunction with the Match Header Mask Register. The IDLEPASS bit in the RXCP Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[3] PTI[2] PTI[1] CLP Default 0 0 0 0 0 0 0 1
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Register 0x68: RXCP Idle Cell Header Mask Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MGFC[3:0]: The MGFC[3:0] bits contain the mask pattern for the first, second, third, and fourth bits of the first octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MPTI[3:0]: The MPTI[3:0] bits contain the mask pattern for the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MCLP: The CLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter. A logic one in this bit position enables the MCLP bit in the pattern register to be compared. A logic zero causes the masking of the MCLP bit. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MGFC[3] MGFC[2] MGFC[1] MGFC[0] MPTI[3] MPTI[2] MPTI[1] MCLP Default 1 1 1 1 1 1 1 1
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Register 0x69: RXCP Corrected HCS Error Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHCS[7:0]: The CHCS[7:0] bits indicate the number of corrected HCS error events that occurred during the last accumulation interval. The contents of these registers are valid a maximum of 40 RCLK periods after a transfer is triggered by a write to one of RXCP's performance monitor counters or to the S/UNI-622-POS Master Reset, and Identity register. Type R R R R R R R R Function CHCS[7] CHCS[6] CHCS[5] CHCS[4] CHCS[3] CHCS[2] CHCS[1] CHCS[0] Default X X X X X X X X
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Register 0x6A: RXCP Uncorrected HCS Error Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UHCS[7:0]: The UHCS[7:0] bits indicate the number of uncorrectable HCS error events that occurred during the last accumulation interval. The contents of these registers are valid a maximum of 40 RCLK periods after a transfer is triggered by a write to one of RXCP's performance monitor counters or to the S/UNI622-POS Master Reset and Identity register. Type R R R R R R R R Function UHCS[7] UHCS[6] UHCS[5] UHCS[4] UHCS[3] UHCS[2] UHCS[1] UHCS[0] Default X X X X X X X X
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Register 0x6B: RXCP Receive Cell Counter LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[7] RCELL[6] RCELL[5] RCELL[4] RCELL[3] RCELL[2] RCELL[1] RCELL[0] Default X X X X X X X X
Register 0x6C: RXCP Receive Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[15] RCELL[14] RCELL[13] RCELL[12] RCELL[11] RCELL[10] RCELL[9] RCELL[8] Default X X X X X X X X
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Register 0x6D: RXCP Receive Cell Counter MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCELL[23:0]: The RCELL[23:0] bits indicate the number of cells received and written into the receive FIFO during the last accumulation interval. Cells received and filtered due to HCS errors or Idle cell matches are not counted. The counter should be polled every second to avoid saturation. The contents of these registers are valid a maximum of 67 RCLK periods after a transfer is triggered by a write to one of RXCP's performance monitor counters or to the S/UNI622-POS Master Reset and Identity register. Type R R R R R R R R Function RCELL[23] RCELL[22] RCELL[21] RCELL[20] RCELL[19] RCELL[18] RCELL[17] RCELL[16] Default X X X X X X X X
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Register 0x6E: RXCP Idle Cell Counter LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function ICELL[7] ICELL[6] ICELL[5] ICELL[4] ICELL[3] ICELL[2] ICELL[1] ICELL[0] Default X X X X X X X X
Register 0x6F: RXCP Idle Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function ICELL[15] ICELL[14] ICELL[13] ICELL[12] ICELL[11] ICELL[10] ICELL[9] ICELL[8] Default X X X X X X X X
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Register 0x70: RXCP Idle Cell Counter MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICELL[23:0]: The ICELL[23:0] bits indicate the number of idle cells received during the last accumulation interval. The counter should be polled every second to avoid saturation. The contents of these registers are valid a maximum of 67 RCLK periods after a transfer is triggered by a write to one of RXCP's performance monitor counters or to the S/UNI-622-POS's Master Reset, and Identity register. Type R R R R R R R R Function ICELL[23] ICELL[22] ICELL[21] ICELL[20] ICELL[19] ICELL[18] ICELL[17] ICELL[16] Default X X X X X X X X
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Register 0x80: TXCP Configuration 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four cell transmit FIFO. When FIFORST is set to logic zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST. Null/unassigned cells are transmitted until a subsequent cell is written to the FIFO. DSCR: The DSCR bit controls the scrambling of the cell payload. When DSCR is a logic one, cell payload scrambling is disabled. When DSCR is a logic zero, payload scrambling is enabled. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to insertion in the synchronous payload envelope. When HCSADD is a logic one, the polynomial is added, and the resulting HCS is inserted. When HCSADD is a logic zero, the polynomial is not added, and the unmodified HCS is inserted. HCSADD takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO. HCSB: The active low HCSB bit enables the internal generation and insertion of the HCS octet into the transmit cell stream. When HCSB is logic zero, the HCS is Type R/W R/W R/W R/W R/W R/W R/W R/W Function TPTYP TCALEVEL0 HSCR Reserved HCSB HCSADD DSCR FIFORST Default 0 0 0 0 0 1 0 0
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generated and inserted internally. If HCSB is logic one, then no HCS octet is inserted in the transmit data stream. HSCR: The Header Scramble enable bit, HSCR, enables scrambling of the ATM five octet header along with the payload. When set to logic one, the ATM header and payload are both scrambled. When set to logic zero, the header is left unscrambled and payload scrambling is determined by the DSCR bit. TCALEVEL0: The TCA level control (TCALEVEL0) determines when the TCA will transition low as the FIFO fills for Level 2 operation. When TCALEVEL0 is logic zero, TCA will deassert on the same rising TFCLK edge that samples word 21 of the 27 word ATM cell structure. When TCALEVEL0 is logic one, TCA will deassert on the same rising TFCLK edge that samples word 26 of the 27 word ATM cell structure. TCALEVEL0 must be set low when the system interface is configured for Level 3 operation. TPTYP: The TPTYP bit selects even or odd parity for input TPRTY for Level 2 operation. When set to logic one, input TPRTY is the even parity bit for the TDAT input bus. When set to logic zero, input TPRTY is the odd parity bit for the TDAT input bus. TPTYP must be set low when the system interface is configured for Level 3 operation. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x81: TXCP Configuration 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCSCTLEB: The active low HCS control enable, HCSCTLEB bit enables the XORing of the HCS Control byte with the generated HCS. When set to logic zero, the HCS Control byte provided in the third word of the 27 word data structure is XORed with the generated HCS. When set to logic one, XORing is disabled and the HCS Control byte is ignored. For normal operation, the HCS Control byte in the ATM cell structure transferred on the system interface should always be 0x00. If not, the HCSCTLEB register should be set to logic one to prevent corruption of the HCS byte. DHCS: The DHCS bit controls the insertion of HCS errors for diagnostic purposes. When DHCS is set to logic one, the HCS octet is inverted prior to insertion in the synchronous payload envelope. DHCS takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO. DHCS occurs after any error insertion caused by the Control Byte in the 27-word data structure. FIFODP[1:0]: The FIFODP[1:0] bits determine the transmit FIFO cell depth at which TCA is de-asserted. FIFO depth control may be important in systems where the cell latency through the TXCP must be minimized. When the FIFO is filled to the specified depth, the transmit cell available signal, TCA is deasserted. Note that regardless of what fill level FIFODP[1:0] is set to, the transmit cell R/W R/W R/W R/W R/W Type Function Unused Unused Unused TCAINV FIFODP[1] FIFODP[0] DHCS HCSCTLEB Default X X X 0 0 0 0 0
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processor can store 4 complete cells. The selectable FIFO cell depths are shown below:
FIFODP[1] 0 0 1 1 FIFODP[0] 0 1 0 1 FIFO DEPTH 4 cells 3 cells 2 cells 1 cell
TCAINV: The TCAINV bit inverts the polarity of the TCA output signal for Level 2 operation. When TCAINV is a logic one, the polarity of TCA is inverted (TCA at logic zero means there is transmit cell space available to be written to). When TCAINV is a logic zero, the polarity of TCA is not inverted. TCAINV must be set low when the system interface is configured for Level 3 operation.
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Register 0x82: TXCP Cell Count Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XFERI: The XFERI bit indicates that a transfer of Transmit Cell Count data has occurred. A logic one in this bit position indicates that the Transmit Cell Count registers have been updated. This update is initiated by writing to one of the Transmit Cell Count register locations or to the S/UNI-622-POS, Master Reset and Identity register. XFERI is set low when this register is read. OVR: The OVR bit is the overrun status of the Transmit Cell Count registers. A logic one in this bit position indicates that a previous transfer (indicated by XFERI being logic one) has not been acknowledged before the next accumulation interval has occurred and that the contents of the Transmit Cell Count registers have been overwritten. OVR is set low when this register is read. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the Transmit Cell Count registers. When XFERE is set high, the interrupt is enabled. Reserved: These bits should be set to their default values for proper operation. R/W R/W R/W R/W Type R/W R R Function XFERE XFERI OVR Unused Reserved Reserved Reserved Reserved Default 0 X X X 1 0 0 0
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Register 0x83: TXCP Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSOCI: The TSOCI bit is set high when the TSOC input is sampled high during any position other than the first word of the selected data structure. The write address counter is reset to the first word of the data structure when TSOC is sampled high. This bit is reset immediately after a read to this register. FOVRI: The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already full. This bit is reset immediately after a read to this register. TPRTYI: The TPRTYI bit indicates if a parity error was detected on the TDAT input bus. When logic one, the TPRTYI bit indicates a parity error over the active TDAT bus. This bit is cleared when this register is read. Odd or even parity is selected using the TPTYP bit. TSOCE: The TSOCE bit enables the generation of an interrupt when the TSOC input is sampled high during any position other than the first word of the selected data structure. When TSOCE is set to logic one, the interrupt is enabled. R R R Type R/W R/W R/W Function TPRTYE FOVRE TSOCE Unused Unused TPRTYI FOVRI TSOCI Default 0 0 0 X X X X X
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FOVRE: The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO when it is already full. When FOVRE is set to logic one, the interrupt is enabled. TPRTYE: The TPRTYE bit enables transmit parity interrupts. When set to logic one, parity errors are indicated on INTB and TPRTYI. When set to logic zero, parity errors are indicated using bit TPRTYI, but are not indicated on output INTB.
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Register 0x84: TXCP Idle Cell Header Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLP: The CLP bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. Cell rate decoupling is accomplished by transmitting idle cells when the TXCP detects that no outstanding cells exist in the transmit FIFO. PTI[3:0]: The PTI[3:0] bits contain the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted when the TXCP detects that no outstanding cells exist in the transmit FIFO. GFC[3:0]: The GFC[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. Idle/unassigned cells are transmitted when the TXCP detects that no outstanding cells exist in the transmit FIFO. The all zeros pattern is transmitted in the VCI and VPI fields of the idle cell. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP Default 0 0 0 0 0 0 0 1
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Register 0x85: TXCP Idle Cell Payload Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAYLD[7:0]: The PAYLD[7:0] bits contain the pattern inserted in the idle cell payload. Idle cells are inserted when the TXCP detects that the transmit FIFO contains no outstanding cells. PAYLD[7] is the most significant bit and is the first bit transmitted. PAYLD[0] is the least significant bit. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PAYLD[7] PAYLD[6] PAYLD[5] PAYLD[4] PAYLD[3] PAYLD[2] PAYLD[1] PAYLD[0] Default 0 1 1 0 1 0 1 0
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Register 0x86: TXCP Transmit Cell Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[7] TCELL[6] TCELL[5] TCELL[4] TCELL[3] TCELL[2] TCELL[1] TCELL[0] Default X X X X X X X X
Register 0x87: TXCP Transmit Cell Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[15] TCELL[14] TCELL[13] TCELL[12] TCELL[11] TCELL[10] TCELL[9] TCELL[8] Default X X X X X X X X
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Register 0x88: TXCP Transmit Cell Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCELL[23:0]: The TCELL[23:0] bits indicate the number of cells read from the transmit FIFO and inserted into the transmission stream during the last accumulation interval. Idle cells inserted into the transmission stream are not counted. A write to any one of the TXCP Transmit Cell Counter registers or to the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 19 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to the Transmit Cell Counter registers. The counter should be polled every second to avoid saturating. The contents of these registers are valid after a maximum of 67 TCLK cycles after a transfer is triggered by a write to a TXCP Transmit Cell count Register or the S/UNI-622POS Master Reset and Identity register. Type R R R R R R R R Function TCELL[23] TCELL[22] TCELL[21] TCELL[20] TCELL[19] TCELL[18] TCELL[17] TCELL[16] Default X X X X X X X X
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Register 0x90: RUL3 Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RSYSSEL: The Receive System Interface Select RSYSSEL allows the SYSSEL pin to be observed and overridden by software. When the RMOVR bit is set low, the RSYSSEL bit is read-only and reports the status of the SYSSEL pin. When RMOVR is set high, the value of the RSYSSEL bit is used to determine the system mode and the SYSEL pin is ignored. When RMOVR is set high and RSYSSEL is set low, the receive side of the system interface is configured for Level 2 operation. When RMOVR is set high and RSYSSEL is set high, the receive side of the system interface is configured for Level 3 operation. RPOS_ATMB: The Receive ATM/POS Mode Select RPOS_ATMB allows the POS_ATMB pin to be observed and overridden by software. When the RMOVR bit is set low, the RPOS_ATMB bit is read-only and reports the status of the POS_ATMB pin. When RMOVR is set high, the value of the RPOS_ATMB bit is used to determine the receive side of the system interface mode and the POS_ATMB pin is ignored. When RMOVR is set high and RPOS_ATMB is set low, the receive side of the system interface is configured for ATM cells. When RMOVR is set high and RPOS_ATMB is set high, the system interface is configured for packet data. RMOVR: The Receive Mode Over-Ride bit RMOVR enables the RSYSSEL and RPOS_ATMB bits to override the mode selected by the SYSSEL and R/W R/W R/W R/W Type Function Unused Unused Unused RL3PP Unused RMOVR RPOS_ATMB RSYSSEL Default X X X 0 X 0 X X
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POS_ATMB pins. When RMOVR is low, the receive side of the system interface is selected by the external pins, and can be read from the RSYSSEL and RPOS_ATMB register bits. When RMOVR is high, the mode is controlled by writing to the RSYSSEL and RPOS_ATMB bits, and the external mode pins are ignored. RL3PP: The Receive Level 3 Parity RL3PP bit selects even or odd parity for output RPRTY when the system interface is configured for Level 3 operation. When set high, output RPRTY is the even parity bit for outputs RDAT[7:0]. When RL3PP is set to low, RPRTY is the odd parity bit for outputs RDAT[7:0]. RL3PP is ignored when the system interface is configured for Level 2 operation. RL3PP is ignored when the system interface is configured for Level 2 operation.
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Register 0x92: TUL3 Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSYSSEL: The Transmit System Interface Select TSYSSEL allows the SYSSEL pin to be observed and overridden by software. When the TMOVR bit is set low, the TSYSSEL bit is read-only and reports the status of the SYSSEL pin. When TMOVR is set high, the value of the TSYSSEL bit is used to determine the system mode and the SYSEL pin is ignored. When TMOVR is set high and TSYSSEL is set low, the transmit side of the system interface is configured for Level 2 operation. When TMOVR is set high and TSYSSEL is set high, the transmit side of the system interface is configured for Level 3 operation. TPOS_ATMB: The Transmit ATM/POS Mode Select TPOS_ATMB allows the POS_ATMB pin to be observed and overridden by software. When the TMOVR bit is set low, the TPOS_ATMB bit is read-only and reports the status of the POS_ATMB pin. When TMOVR is set high, the value of the RPOS_ATMB bit is used to determine the system interface mode and the POS_ATMB pin is ignored. When TMOVR is set high and TPOS_ATMB is set low, the transmit side of the system interface is configured for ATM cells. When TMOVR is set high and TPOS_ATMB is set high, the transmit side of the system interface is configured for packet data. TMOVR: The Transmit Mode Over-Ride bit TMOVR enables the TSYSSEL and TPOS_ATMB bits to override the mode selected by the SYSSEL and R/W R/W R/W R/W Type Function Unused Unused Unused TL3PP Unused TMOVR TPOS_ATMB TSYSSEL Default X X X 0 X 0 X X
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POS_ATMB pins. When TMOVR is low, the system interface mode is selected by the external pins, and can be read from the TSYSSEL and TPOS_ATMB register bits. When TMOVR is high, the mode is controlled by writing to the TSYSSEL and TPOS_ATMB bits, and the external mode pins are ignored. TL3PP: The Transmit Level 3 Parity TL3PP bit selects even or odd parity for input RPRTY when the system interface is configured for Level 3 operation. When set high, input TPRTY is the even parity bit for inputs TDAT[7:0]. When TL3PP is set to low, TPRTY is the odd parity bit for input RDAT[7:0]. TL3PP is ignored when the system interface is configured for Level 2 operation. TL3PP is ignored when the system interface is configured for Level 2 operation.
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Register 0x94: DLL RUL3 Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused Reserved Unused Unused Reserved Reserved Default X X X 0 X X 0 0
The DLL Configuration Register controls the basic operation of the DLL for the receive system interface clock RFCLK.
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Register 0x96: DLL RUL3 Delay Tap Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default X X X X X X X X
Writing to this register performs a software reset of the DLL. The software reset will disrupt the Receive Level 2/3 interface controlled by RFCLK clock. Any FIFOs associated with the RFCLK (RXCP and RXFP) must be reset using FIFORST after the DLL is reset.
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Register 0x97: DLL RUL3 Control Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R Type R R R R Function RFCLKI Reserved ERRORI Reserved Unused ERROR Reserved RUN Default X X X X X X X X
The DLL Control Status Register provides information of the DLL operation. RUN: The DLL lock status register bit RUN indicates the DLL has found an initial lock condition. When the phase detector first indicates lock, RUN is set high. The RUN register bit is cleared only by a system reset or a software reset.
ERROR: The delay line error register ERROR indicates the DLL is currently at the end of the delay line. ERROR is set high when the DLL tries to move beyond the end of the delay line.
ERRORI: The error event register bit ERRORI indicates the ERROR register bit has been a logic one. When the ERROR register changes from a logic zero to a logic one, the ERRORI register bit is set to logic one. The ERRORI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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RFCLKI: The clock event register bit RFCLKI provides a method to monitor activity on the RFCLK clock. When the RFCLK input changes from a logic zero to a logic one, the RFCLKI register bit is set to logic one. The RFCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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Register 0x98: DLL TUL3 Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused Reserved Unused Unused Reserved Reserved Default X X X 0 X X 0 0
The DLL Configuration Register controls the basic operation of the DLL for the receive system interface clock TFCLK.
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Register 0x9A: DLL TUL3 Delay Tap Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default X X X X X X X X
Writing to this register performs a software reset of the DLL. The software reset will disrupt the Transmit Level 2/3 interface controlled by TFCLK clock. Any FIFOs associated with the TFCLK (TXCP and TXFP) must be reset using FIFORST after the DLL is reset.
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Register 0x9B: DLL TUL3 Control Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R Type R R R R Function TFCLKI Reserved ERRORI Reserved Unused ERROR Reserved RUN Default X X X X X X X X
The DLL Control Status Register provides information of the DLL operation. RUN: The DLL lock status register bit RUN indicates the DLL has found an initial lock condition. When the phase detector first indicates lock, RUN is set high. The RUN register bit is cleared only by a system reset or a software reset.
ERROR: The delay line error register ERROR indicates the DLL is currently at the end of the delay line. ERROR is set high when the DLL tries to move beyond the end of the delay line.
ERRORI: The error event register bit ERRORI indicates the ERROR register bit has been a logic one. When the ERROR register changes from a logic zero to a logic one, the ERRORI register bit is set to logic one. The ERRORI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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TFCLKI: The clock event register bit TFCLKI provides a method to monitor activity on the TFCLK clock. When the TFCLK input changes from a logic zero to a logic one, the TFCLKI register bit is set to logic one. The TFCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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Register 0x9C: DLL Parallel Transmit Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused OVERRIDE Unused Unused Reserved Reserved Default X X X 0 X X 0 0
The DLL Configuration Register controls the basic operation of the DLL for the receive system interface clock PTCLK.
OVERRIDE: The override control (OVERRIDE) disables the DLL operation. When OVERRIDE is set low, the DLL generates the internal clock by delaying the PTCLK to ensure the best possible output propagation on the system interface. When OVERRIDE is set high, the system interface output propagation will not meet the specified timing. This feature provides a backup strategy for very low frequency PTCLK operation.
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Register 0x9E: DLL Parallel Transmit Delay Tap Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default X X X X X X X X
Writing to this register performs a software reset of the DLL. The software reset will disrupt the Transmit parallel interface controlled by PTCLK clock.
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Register 0x9F: DLL Parallel Transmit Control Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R Type R R R R Function PTCLKI Reserved ERRORI Reserved Unused ERROR Reserved RUN Default X X X X X X X X
The DLL Control Status Register provides information of the DLL operation. RUN: The DLL lock status register bit RUN indicates the DLL has found an initial lock condition. When the phase detector first indicates lock, RUN is set high. The RUN register bit is cleared only by a system reset or a software reset.
ERROR: The delay line error register ERROR indicates the DLL is currently at the end of the delay line. ERROR is set high when the DLL tries to move beyond the end of the delay line.
ERRORI: The error event register bit ERRORI indicates the ERROR register bit has been a logic one. When the ERROR register changes from a logic zero to a logic one, the ERRORI register bit is set to logic one. The ERRORI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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PTCLKI: The clock event register bit PTCLKI provides a method to monitor activity on the PTCLK clock. When the PTCLK input changes from a logic zero to a logic one, the PTCLKI register bit is set to logic one. The PTCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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Register 0xA0: RXFP Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the 256-byte receive FIFO. When FIFORST is set low, the FIFO operates normally. When FIFORST is set high, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST. DDSCR: The DDSCR bit controls the descrambling of the frame payload with the polynomial x43 + 1. When DDSCR is set low, frame payload descrambling is disabled. When DDSCR is set high, payload descrambling is enabled. RXPTYP: The RXPTYP bit selects even or odd parity for output RPRTY for Level 2 operation. When set high, output RPRTY is the even parity bit for outputs RDAT[15:0]. When RXPTYP is set low, RPRTY is the odd parity bit for outputs RDAT[15:0]. RXPTYP must be set low when the system interface is configured for Level 3 operation. FCSSEL[1:0]: The Frame Control Sequence select (FCSSEL[1:0]) bits control the FCS calculation according to the table below. The FCS is calculated over the whole packet data, after byte destuffing and descrambling. Type
R/W
Function
Reserved
Default
0
R/W R/W R/W R/W R/W R/W R/W
FCSPASS RPAINV FCSSEL[1] FCSSEL[0] RXPTYP DDSCR FIFORST
0 0 1 0 0 1 0
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FCSSEL[1:0] 00
01 10 11
FCS Operation No FCS calculated CRC-CCITT (2 bytes) CRC-32 (4 bytes) Reserved
RPAINV: The RPAINV bit inverts the polarity of the RPA output signal for Level 2 operation. When RPAINV is a logic one, the polarity of RPA is inverted (RPA at logic zero means there is a receive cell available to be read). When RPAINV is a logic zero, the polarity of RPA is not inverted. RPAINV must be set low when the system interface is configured for Level 3 operation. FCSPASS: FCSPASS determines if the FCS field will be passed through the system interface or stripped. When FCSPASS is set to logic one, the POS frame FCS field is written into the FIFO as part of the packet, and can thus be read through the system interface. When FCSPASS is set to logic zero, the FCS field is stripped from the POS frame. Reserved: The reserved bit must be programmed to logic zero for proper operation.
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Register 0xA1: RXFP Configuration/Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FOVRE: The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition. When FOVRE is set high, the interrupt is enabled. FCSE: The FCSE bit enables the generation of an interrupt due to the detection of an FCS error. When FCSE is set high, the interrupt is enabled. ABRTE: The Abort Packet Enable bit enables the generation of an interrupt due to the reception of an aborted packet. When ABRTE is set high, the interrupt is enabled. MAXLE: The Maximum Length Packet Enable bit enables the generation of an interrupt due to the reception of a packet exceeding the programmable maximum packet length. When MAXLE is set high, the interrupt is enabled. MINLE: The Minimum Length Packet Enable bit enables the generation of an interrupt due to the reception of a packet that is smaller than the programmable minimum packet length. When MINLE is set high, the interrupt is enabled. Reserved: The reserved bit must be programmed to logic zero for proper operation. R/W R/W R/W R/W R/W R/W Type Function Unused Unused MINLE MAXLE ABRTE FCSE FOVRE Reserved Default X X 0 0 0 0 0 0
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Register 0xA2: RXFP Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FOVRI: The FOVRI bit indicates an interrupt due to a FIFO overrun error condition. This interrupt can be masked using FOVRE. FCSI: The FCSI bit indicates an interrupt due to the detection of an FCS error. This interrupt can be masked using FCSE. ABRTI: The ABRTI bit indicates the generation of an interrupt due to the reception of an aborted packet. This interrupt can be masked using ABRTE. MAXLI: The MAXLI bit indicates an interrupt due to the reception of a packet exceeding the programmable maximum packet length. This interrupt can be masked using MAXLE. MINLI: The MINLI bit indicates an interrupt due to the reception of a packet that is smaller than the programmable minimum packet length. This interrupt can be masked using MINLE. R R R R R Type Function Unused Unused MINLI MAXLI ABRTI FCSI FOVRI Unused Default X X X X X X X X
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Register 0xA3: RXFP Minimum Packet Length Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MINPL[7:0]: The Minimum Packet Length (MINPL[7:0]) bits are used to set the minimum packet length. Packets smaller than this length are marked with an error. The packet length used here is defined as the number of bytes encapsulated into the POS frame, including the FCS but excluding byte stuffing. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MINPL[7] MINPL[6] MINPL[5] MINPL[4] MINPL[3] MINPL[2] MINPL[1] MINPL[0] Default 0 0 0 0 0 1 0 0
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Register 0xA4: RXFP Maximum Packet Length LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function MAXPL[7] MAXPL[6] MAXPL[5] MAXPL[4] MAXPL[3] MAXPL[2] MAXPL[1] MAXPL[0] Default 0 0 0 0 0 0 0 0
Register 0xA5: RXFP Maximum Packet Length MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function MAXPL[15] MAXPL[14] MAXPL[13] MAXPL[12] MAXPL[11] MAXPL[10] MAXPL[9] MAXPL[8] Default 0 0 0 0 0 1 1 0
MAXPL[15:0]: The Maximum Packet Length (MAXPL[15:0]) bits are used to set the maximum packet length. Packets larger than this length are marked with an error. The packet length used here is defined as the number of bytes encapsulated into the POS frame, including the FCS but excluding byte stuffing. The maximum packet length supported by the RXFP is 65534 bytes (0xFFFE).
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Register 0xA6: RXFP Receive Initiation Level Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RIL[3:0]: The Reception Initiation Level (RIL[3:0]) bits are used to set the minimum number of bytes that must be available in the FIFO before received packets can be written into it. RIL[3:0] is only used after a FIFO overrun has been detected and FIFO writes have been suspended. This avoids restarting the reception of data too quickly after an overrun condition. If the system does not cause any FIFO overrun, then this register will not be used. RIL[3:0] breaks the FIFO in 16 sections; for example a value of 0x4 correspond to a FIFO level of 64 bytes. The value of RIL must not be too large in order to prevent repetitive FIFO overruns. Table 7: Receive Initiation Level Values
RIL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 FIFO Fill Level 0 16 32 RIL[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 FIFO Fill Level 128 144 160 176 192 208 224 240
Type R/W R/W R/W R/W R/W R/W R/W R/W
Function Reserved Reserved Reserved Reserved RIL[3] RIL[2] RIL[1] RIL[0]
Default 1 0 0 0 1 1 0 0
48
64 80 96 112
Reserved: These bits must be programmed as indicated by the default column.
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Register 0xA7: RXFP Receive Packet Available High Water Mark Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function RPAHWM[7] RPAHWM[6] RPAHWM[5] RPAHWM[4] RPAHWM[3] RPAHWM[2] RPAHWM[1] RPAHWM[0] Default 0 1 0 0 0 0 0 0
RPAHWM[7:0]: The Receive FIFO High Water Mark (RPAHWM[7:0]) bits are used to generate the RPA output in POS-PHY Level 2 interface. RPA is set to logic one when the number of bytes stored in the FIFO exceeds RPAHWM[7:0] or when there is at least one end of packet in the FIFO. The RPAHWM value is used to determine when data is transferred on the POS-PHY Level 3 interface. The programmed value for RPAHWM[7:0] must be less than 0xF0 and greater than 0x00 for proper operation. When a packet with less than 6 bytes arrives (from the line side), the receive packet available signal (RPA) may assert before data is available. In this condition, RPA will assert between 1 to 3 RFCLK clock cycles before the data is available and will remain asserted for 1 to 3 RFCLK clock cycles. When the Link Layer device attempts to read the packet by asserting read enable (RENB), it may find that there is no valid data available (receive data valid signal (RVAL) remains de-asserted). RPA will correctly assert again later when data is available. At this time the RVAL signal will be asserted indicating valid data. With packets greater than 6 bytes, the RPA signal will assert, de-assert and then reassert 1 to 3 RFCLK cycles later (same as the above case with packets less than 6 bytes). However, if the Link layer device attempts to read the packet on the basis of the first occurrence of RPA, it will read valid data (RVAL will be asserted), even if RPA may be de-asserted.
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This early assertion of RPA will not cause any data corruption if RVAL is used to qualify the data that is read. It is recommended that RVAL always be used to qualify receive data. The operation of RPA may cause a slight reduction bandwidth on receive side of the POS-PHY interface. However, since there is ample bandwidth on the POS-PHY interface there will be no impact on performance of functionality.
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Register 0xA8: RXFP Receive Byte Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RBYTE[7] RBYTE[6] RBYTE[5] RBYTE[4] RBYTE[3] RBYTE[2] RBYTE[1] RBYTE[0] Default X X X X X X X X
Register 0xA9: RXFP Receive Byte Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RBYTE[15] RBYTE[14] RBYTE[13] RBYTE[12] RBYTE[11] RBYTE[10] RBYTE[9] RBYTE[8] Default X X X X X X X X
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Register 0xAA: RXFP Receive Byte Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RBYTE[23] RBYTE[22] RBYTE[21] RBYTE[20] RBYTE[19] RBYTE[18] RBYTE[17] RBYTE[16] Default X X X X X X X X
Register 0xAB: RXFP Receive Byte Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBYTE[31:0]: The RBYTE[31:0] bits indicate the number of received bytes written into the receive FIFO during the last accumulation interval. This counter does not count any byte from errored and aborted frames. A write to any one of the RXFP Receive Byte Counter registers or the S/UNI622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 24 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to the Receive Byte Counter registers. The counter should be polled every second to avoid saturating. The contents of these Type R R R R R R R R Function RBYTE[31] RBYTE[30] RBYTE[29] RBYTE[28] RBYTE[27] RBYTE[26] RBYTE[25] RBYTE[24] Default X X X X X X X X
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registers are valid three RCLK cycles after a transfer is triggered by a write to any of the RXFP Receive Frame Count Registers.
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Register 0xAC: RXFP Receive Frame Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RFRAME[7] RFRAME[6] RFRAME[5] RFRAME[4] RFRAME[3] RFRAME[2] RFRAME[1] RFRAME[0] Default X X X X X X X X
Register 0xAD: RXFP Receive Frame Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RFRAME[15] RFRAME[14] RFRAME[13] RFRAME[12] RFRAME[11] RFRAME[10] RFRAME[9] RFRAME[8] Default X X X X X X X X
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Register 0xAE: RXFP Receive Frame Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RFRAME[23] RFRAME[22] RFRAME[21] RFRAME[20] RFRAME[19] RFRAME[18] RFRAME[17] RFRAME[16] Default X X X X X X X X
RFRAME[23:0]: The RFRAME[23:0] bits indicate the number of successfully received POS frames written into the receive FIFO after their extraction from the SONET/SDH stream during the last accumulation interval. This counter does not count any errored and aborted frames. A write to any one of the RXFP Receive Frame Counter registers or S/UNI622-POS the Master Reset and Identity register loads the registers with the current counter value and resets the internal 24 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to the Receive Frame Counter registers. The counter should be polled every second to avoid saturating. The contents of these registers are valid three RCLK cycles after a transfer is triggered by a write to any of the RXFP Receive Frame Count Registers.
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Register 0xAF: RXFP Receive Aborted Frame Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RABRF[7] RABRF[6] RABRF[5] RABRF[4] RABRF[3] RABRF[2] RABRF[1] RABRF[0] Default X X X X X X X X
Register 0xB0: RXFP Receive Aborted Frame Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RABRF[15:0]: The RABRF[15:0] bits indicate the number of aborted POS frames received and written into the receive FIFO during the last accumulation interval. A write to any one of the RXFP Receive Aborted Frame Counter registers or the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 16 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to these registers. The counter should be polled every second to avoid saturating. The contents of these registers are valid three RCLK cycles after a transfer is triggered. Type R R R R R R R R Function RABRF[15] RABRF[14] RABRF[13] RABRF[12] RABRF[11] RABRF[10] RABRF[9] RABRF[8] Default X X X X X X X X
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Register 0xB1: RXFP Receive FCS Error Frame Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RFCSEF[7] RFCSEF[6] RFCSEF[5] RFCSEF[4] RFCSEF[3] RFCSEF[2] RFCSEF[1] RFCSEF[0] Default X X X X X X X X
Register 0xB2: RXFP Receive FCS Error Frame Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RFCSEF[15] RFCSEF[14] RFCSEF[13] RFCSEF[12] RFCSEF[11] RFCSEF[10] RFCSEF[9] RFCSEF[8] Default X X X X X X X X
RFCSEF[15:0]: The RFCSEF[15:0] bits indicate the number of POS frames received with an FCS error and written into the receive FIFO during the last accumulation interval. A write to any one of the RXFP Receive FCS Error Frame Counter registers or the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 16 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to these registers. The counter should be polled every
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second to avoid saturating. The contents of these registers are valid three RCLK cycles after a transfer is triggered.
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Register 0xB3: RXFP Receive Minimum Length Error Frame Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RMINLF[7] RMINLF[6] RMINLF[5] RMINLF[4] RMINLF[3] RMINLF[2] RMINLF[1] RMINLF[0] Default X X X X X X X X
Register 0xB4: RXFP Receive Minimum Length Error Frame Counter MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RMINLF[15:0]: The RMINLF[15:0] bits indicate the number of minimum packet length POS frames received and written into the receive FIFO during the last accumulation interval. A write to any one of the RXFP Minimum Length Error Frame Counter registers or the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 16 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to these registers. The counter should be Type R R R R R R R R Function RMINLF[15] RMINLF[14] RMINLF[13] RMINLF[12] RMINLF[11] RMINLF[10] RMINLF[9] RMINLF[8] Default X X X X X X X X
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polled every second to avoid saturating. The contents of these registers are valid three RCLK cycles after a transfer is triggered.
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Register 0xB5: RXFP Receive Maximum Length Error Frame Counter LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RMAXLF[7] RMAXLF[6] RMAXLF[5] RMAXLF[4] RMAXLF[3] RMAXLF[2] RMAXLF[1] RMAXLF[0] Default X X X X X X X X
Register 0xB6: RXFP Receive Maximum Length Error Frame Counter MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RMAXLF[15] RMAXLF[14] RMAXLF[13] RMAXLF[12] RMAXLF[11] RMAXLF[10] RMAXLF[9] RMAXLF[8] Default X X X X X X X X
RMAXLF[15:0]: The RMAXLF[15:0] bits indicate the number of POS frames exceeding the maximum packet length that were received and written into the receive FIFO during the last accumulation interval. A write to any one of the RXFP Receive Maximum Length Error Frame Counter registers or the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 16 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to these registers. The counter
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should be polled every second to avoid saturating. The contents of these registers are valid three RCLK cycles after a transfer is triggered.
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Register 0xC0: TXFP Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TPRTYI: The TPRTYI bit indicates if a parity error was detected on the TDAT system interface bus. When logic one, the TPRTYI bit indicates a parity error over the TDAT[15:0] bus. This bit is cleared when this register is read. Odd or even parity is selected using the TPTYP bit. TPRTYE: The TPRTYE bit enables transmit parity interrupts. When set to logic one, parity errors are indicated on INTB and TPRTYI. When set to logic zero, parity errors are indicated using bit TPRTYI, but are not indicated on output INTB. FOVRI: The FOVRI bit is set high when an attempt is made to write into the FIFO while it has already been filled-up. This is considered a system error. This bit is reset immediately after a read to this register. FOVRE: The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO when it is already full. When FOVRE is set to logic one, the interrupt is enabled and causes FOVRI and an interrupt is asserted. When set to logic zero, FOVRI will be asserted but not INTB. Type R/W R R/W R R/W R R/W R Function Reserved FIFOERR FUDRE FUDRI FOVRE FOVRI TPRTYE TPRTYI Default 0 X 0 X 0 X 0 X
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FUDRI: The FUDRI bit is set high when the FIFO underruns while reading a packet data from the FIFO. This bit is reset immediately after a read to this register. FUDRE: The FUDRE bit enables the generation of an interrupt due to a FIFO underrun. When FUDRE is set to logic one, the interrupt is enabled and causes FUDRI and the output INTB to be asserted. When set to logic zero, FUDRI will be asserted, but not INTB. FIFOERR: The FIFOERR bit is set high when a packet is not properly delineated by a RSOP and REOP pair on the system interface. If the FIFO sees two start of packet indications (RSOP high) or two end of packet indications (REOP high), the current packet is aborted and FIFOERR is set high. This bit is reset immediately after a read to this register. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0xC1: TXFP Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the 256-byte transmit FIFO. When FIFORST is set to logic zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is emptied of all octets (including the current packet being transmitted) and ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST. Flags are transmitted until a subsequent packet is written to the FIFO. DSCR: The DSCR bit controls the scrambling of the POS frames. When DSCR is a logic one, scrambling is enabled. When DSCR is a logic zero, payload scrambling is disabled. TPTYP: The TPTYP bit selects even or odd parity for input TPRTY for Level 2 operation. When set to logic one, the TPRTY input must report even parity for the TDAT system interface bus. When set to logic zero, input TPRTY must report odd parity for the TDAT bus. TPTYP must be set low when the system interface is configured for Level 3 operation. FCSSEL[1:0]: The Frame Control Sequence select (FCSSEL[1:0]) bits control the FCS calculation according to the table below. The FCS is calculated over the Type R/W R/W R/W R/W R/W R/W R/W R/W Function XOFF TPAINV FCSERR FCSSEL[1] FCSSEL[0] TPTYP DSCR FIFORST Default 0 0 0 1 0 0 1 0
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whole packet data, before byte stuffing and scrambling.
FCSSEL[1:0] 00 01 10 11 FCS Operation No FCS inserted CRC-CCITT (2 bytes) CRC-32 (4 bytes) Reserved
FCSERR: The FCSERR bit controls the insertion of FCS errors for diagnostic purposes. When FCSERR is set to logic one, if FCS insertion is enabled, the FCS octets are inverted prior to insertion in the POS frame. When FCSERR is set low, the FCS is inserted normally. TPAINV: The TPAINV bit inverts the polarity of the TPA output signal for Level 2 operation. When TPAINV is a logic one, the polarity of TPA is inverted. When TPAINV is a logic zero, TPA operates normally. TPAINV must be set low when the system interface is configured for Level 3 operation. XOFF: The XOFF serves as a transmission enable bit. When XOFF is set to logic zero, POS frames are transmitted normally. When XOFF is set to logic one, the current frame being transmitted is completed and then POS frame transmission is suspended. When XOFF is asserted the FIFO still accepts data and can overflow. XOFF is provided to facilitate system debugging rather than flow control, which is better achieved using inter-packet gapping.
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Register 0xC2: TXFP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIL[3:0]: The Transmit Initiation Level (TIL[3:0]) bits are used to determine when to initiate a POS frame transmission. After the FIFO is emptied, data transmission starts only when either there is a complete packet or when the number of bytes stored in the FIFO exceeds the value of TIL[3:0] times 16. Once initiated, the transmission will continue until the packet is transmitted or an underrun occurs. Before starting another packet, a complete packet must be in the FIFO or the FIFO fill level must exceed the level specified by TIL[3:0]. TIL[3:0] breaks the FIFO in 16 sections; for example a value of 0x4 correspond to a FIFO level of 64 bytes. Table 8: Transmit Initiation Level Values
TIL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 FIFO Fill Level 0 16 TIL[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 FIFO Fill Level 128 144 160 176 192 208 224 240
Type R/W R/W R/W R/W R/W R/W R/W R/W
Function IPGAP[3] IPGAP[2] IPGAP[1] IPGAP[0] TIL[3] TIL[2] TIL[1] TIL[0]
Default 0 0 1 0 0 1 0 0
32
48 64 80 96 112
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IPGAP[3:0]: The Inter Packet Gaping (IPGAP[3:0]) bits are used to program the number of Flag Sequence characters inserted between each POS Frame. The programmed value is encoded as indicated in Table 9. Table 9: Inter Packet Gaping Values
IPGAP[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Number of Flag 1 2 4 8 16 32 64 128 IPGAP[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Number of Flag 256 512 1024 2048
4096
8192 16384 32768
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Register 0xC3: TXFP Transmit Packet Available Low Water Mark Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TPALWM[7] TPALWM[6] TPALWM[5] TPALWM[4] TPALWM[3] TPALWM[2] TPALWM[1] TPALWM[0] Default 0 1 0 0 0 0 0 0
TPALWM[7:0]: The Transmit FIFO Low Water Mark (TPALWM[7:0]) bits are used to generate the TPA output. TPALWM must not be programmed with a value less than 0x0F for proper operation. Due to internal pipeline delay, the TPA output may not assert until the FIFO level has dropped a maximum of 16 bytes below the value specified by TPALWM. For Level 2 system interfaces, TPA is set to logic one when the number of bytes stored in the FIFO is lower than TPALWM[7:0]. For Level 3 system interfaces, TPA is set to logic one when the number of bytes sorted in the FIFO is lower than TPALWM[7:0] plus 2 bytes.
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Register 0xC4: TXFP Transmit Packet Available High Water Mark Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TPAHWM[7] TPAHWM[6] TPAHWM[5] TPAHWM[4] TPAHWM[3] TPAHWM[2] TPAHWM[1] TPAHWM[0] Default 1 1 1 1 0 0 0 0
TPAHWM[7:0]: The Transmit FIFO High Water Mark (TPAHWM[7:0]) bits are used to generate the TPA output. TPAHWM must not be programmed with a value greater than 0xF0 for proper operation. Due to internal pipeline delay, the TPA output may not deassert until the FIFO level has raised a maximum of 8 bytes above the value specified by TPAHWM. For Level 2 system interfaces, TPA is set to logic zero when the number of bytes stored in the FIFO exceeds TPAHWM[7:0]. For Level 3 system interfaces, TPA is set to logic zero when the number of bytes stored in the FIFO exceeds TPAHWM[7:0] less four bytes.
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Register 0xC5: TXFP Transmit Byte Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TBYTE[7] TBYTE[6] TBYTE[5] TBYTE[4] TBYTE[3] TBYTE[2] TBYTE[1] TBYTE[0] Default X X X X X X X X
Register 0xC6: TXFP Transmit Byte Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TBYTE[15] TBYTE[14] TBYTE[13] TBYTE[12] TBYTE[11] TBYTE[10] TBYTE[9] TBYTE[8] Default X X X X X X X X
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Register 0xC7: TXFP Transmit Byte Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TBYTE[23] TBYTE[22] TBYTE[21] TBYTE[20] TBYTE[19] TBYTE[18] TBYTE[17] TBYTE[16] Default X X X X X X X X
Register 0xC8: TXFP Transmit Byte Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBYTE[31:0]: The TBYTE[31:0] bits indicate the number of bytes read from the transmit FIFO and transmitted during the last accumulation interval. This counter does not count bytes within aborted frames. A write to any one of the TXFP Transmit Byte Counter registers or the S/UNI622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 32 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to the Transmit Byte Counter registers. The counter should be polled every second to avoid saturating. The contents of these Type R R R R R R R R Function TBYTE[31] TBYTE[30] TBYTE[29] TBYTE[28] TBYTE[27] TBYTE[26] TBYTE[25] TBYTE[24] Default X X X X X X X X
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registers are valid three TCLK cycles after a transfer is triggered by a write to any of the TXFP Transmit Byte Count Registers.
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Register 0xC9: TXFP Transmit Frame Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TFRAME[7] TFRAME[6] TFRAME[5] TFRAME[4] TFRAME[3] TFRAME[2] TFRAME[1] TFRAME[0] Default X X X X X X X X
Register 0xCA: TXFP Transmit Frame Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TFRAME[15] TFRAME[14] TFRAME[13] TFRAME[12] TFRAME[11] TFRAME[10] TFRAME[9] TFRAME[8] Default X X X X X X X X
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Register 0xCB: TXFP Transmit Frame Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TFRAME[23] TFRAME[22] TFRAME[21] TFRAME[20] TFRAME[19] TFRAME[18] TFRAME[17] TFRAME[16] Default X X X X X X X X
TFRAME[23:0]: The TFRAME[23:0] bits indicate the number of POS frames read from the transmit FIFO and inserted into the transmission stream during the last accumulation interval. This counter does not count aborted frames. A write to any one of the TXFP Transmit Frame Counter registers or the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 24 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to the Transmit Frame Counter registers. The counter should be polled every second to avoid saturating. The contents of these registers are valid three TCLK cycles after a transfer is triggered by a write to any of the TXFP Transmit Frame Count Registers.
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Register 0xCC: TXFP Transmit User Aborted Frame Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TUSRABF[7] TUSRABF[6] TUSRABF[5] TUSRABF[4] TUSRABF[3] TUSRABF[2] TUSRABF[1] TUSRABF[0] Default X X X X X X X X
Register 0xCD: TXFP Transmit User Aborted Frame Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TUSRABF[15] TUSRABF[14] TUSRABF[13] TUSRABF[12] TUSRABF[11] TUSRABF[10] TUSRABF[9] TUSRABF[8] Default X X X X X X X X
TUSRABF[15:0]: The TUSRABF[15:0] bits indicate the number of user aborted POS frames read from the transmit FIFO and inserted into the transmission stream during the last accumulation interval. User can abort frames by asserting TERR. A write to any one of the TXFP Transmit User Aborted Frame Counter registers or the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 16 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to these registers. The counter should be
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polled every second to avoid saturating. The contents of these registers are valid three TCLK cycles after a transfer is triggered.
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Register 0xCE: TXFP Transmit Underrun/Error Aborted Frame Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TFERABF[7] TFERABF[6] TFERABF[5] TFERABF[4] TFERABF[3] TFERABF[2] TFERABF[1] TFERABF[0] Default X X X X X X X X
Register 0xCF: TXFP Transmit Underrun/Error Aborted Frame Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TFERABF[15] TFERABF[14] TFERABF[13] TFERABF[12] TFERABF[11] TFERABF[10] TFERABF[9] TFERABF[8] Default X X X X X X X X
TRERABF[15:0]: The TFERABF[15:0] bits indicate the number of FIFO underrun error aborted POS frames read from the transmit FIFO and inserted into the transmission stream during the last accumulation interval. FIFO underruns errors are caused when the FIFO runs empty and the last byte read was not an end of packet or also when the FIFO overruns and corrupts the end of packet/start of packet sequence (example: when another RSOP is high when expecting an REOP). This is considered a system error and should not occur when the system works normally.
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A write to any one of the TXFP Transmit User Aborted Frame Counter registers or the S/UNI-622-POS Master Reset and Identity register loads the registers with the current counter value and resets the internal 16 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to these registers. The counter should be polled every second to avoid saturating. The contents of these registers are valid three TCLK cycles after a transfer is triggered.
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Register 0xD0: WANS Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W Function Reserved Unused Unused Unused FORCEREAC AUTOREAC INTEN PHACOMPEN Default 0 X X X 0 0 0 0
PHACOMPEN: The Phase Comparison Enable (PHACOMPEN) bit is used to enable the phase comparison process. Setting this bit to a logic one will enable the phase comparison process. When set low, the phase and reference period counters are kept in reset state, further disabling the WANS process INTEN: The Interrupt Enable (INTEN) bit controls the generation of the interrupt signal. When set high, this bit allows the generation of an interrupt signal at the beginning of the Phase Detector averaging period. Setting this bit to logic zero disables the generation of the interrupts. AUTOREAC: The Auto Reacquisition Mode Select (AUTOREAC) bit can be used to set the WANS to automatic phase reacquisition mode. When operating in this mode, the WANS will automatically align the phase sampling point toward the middle of the Phase Counter period upon detection of two consecutive Phase Sample located on each side of the Phase Counter wrap around value. The Phase Word register will keep its previous value till. Setting this bit to logic one enables the automatic reacquisition mode. FORCEREAC: The Force Phase Reacquisition (FORCEREAC) bit can be used to force a phase reacquisition of the Phase Detector. A logic zero to logic one transition
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on this bit triggers a phase reacquisition sequence of the Phase Detector. Setting this bit to logic zero allows the Phase detector to operate normally. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0xD1: WANS Interrupt and Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIMI: The Timer Interrupt (TIMI) bit indicates a Timer Interrupt condition. This bit will be raised at the beginning of the Phase Detector averaging period. In addition to indicating the interrupt status, this bit can also be polled to synchronize read access to the WANS output register. This interrupt can be masked using the INTEN bit of the configuration register. A read access to the Interrupt & Status Register resets the value of this bit. RPHALGN: The Reference Phase Alignment (RPHALNG) bit indicates a Reference Phase Alignment event. In normal operating mode, this bit remains set to logic zero. Upon the occurrence of a Reference Phase Alignment, this bit is set to logic one, indicating that the phase averaging process was aborted and that the value of the Phase Word register is frozen to the previous valid value. This bit is reset low after the completion of a valid phase averaging cycle. R R Type Function Unused Unused Unused Unused Unused Unused RPHALGN TIMI Default X X X X X X X X
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Register 0xD2: WANS Phase Word LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PHAWORD[7] PHAWORD[6] PHAWORD[5] PHAWORD[4] PHAWORD[3] PHAWORD[2] PHAWORD[1] PHAWORD[0] Default X X X X X X X X
Register 0xD3: WANS Phase Word Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PHAWORD[15] PHAWORD[14] PHAWORD[13] PHAWORD[12] PHAWORD[11] PHAWORD[10] PHAWORD[9] PHAWORD[8] Default X X X X X X X X
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Register 0xD4: WANS Phase Word Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PHAWORD[23] PHAWORD[22] PHAWORD[21] PHAWORD[20] PHAWORD[19] PHAWORD[18] PHAWORD[17] PHAWORD[16] Default X X X X X X X X
Register 0xD5: WANS Phase Word MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused PHAWORD[30] PHAWORD[29] PHAWORD[28] PHAWORD[27] PHAWORD[26] PHAWORD[25] PHAWORD[24] Default X X X X X X X X
PHAWORD[30:0]: The Phase Word (PHAWORD[30:0]) bits are the output bus of the Phase Detector. This bus outputs the result of the Phase Count Averaging function. Depending on the number of samples included in the averaging, from 0 to 15 of the LSB(s) of the PHAWORD bus may represent the fractional part of the average value while the 16 following bits hold the integer part. This value can be used to externally implement in software the PLL filtering function and bypass the Digital Loop Filter block.
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Register 0xD9: WANS Reference Period LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function REFPER[7] REFPER[6] REFPER[5] REFPER[4] REFPER[3] REFPER[2] REFPER[1] REFPER[0] Default 0 0 0 0 0 0 0 0
Register 0xDA: WANS Reference Period MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function REFPER[15] REFPER[14] REFPER[13] REFPER[12] REFPER[11] REFPER[10] REFPER[9] REFPER[8] Default 0 0 0 0 0 0 0 0
REFPER[15:0]: The Reference Period REFPER[15:0] bits are used to program the timing reference period of the Phase Detector. These bits are used to set the end of count of the Reference Period Counter. The Reference Period Counter is reset on the next clock cycle following the detection of its end of count. The Reference Period Counter counts (Nref) is equal to the REFPER value plus 1.
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Register 0xDB: WANS Phase Counter Period LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PHCNTPER[7] PHCNTPER[6] PHCNTPER[5] PHCNTPER[4] PHCNTPER[3] PHCNTPER[2] PHCNTPER[1] PHCNTPER[0] Default 0 0 0 0 0 0 0 0
Register 0xDC: WANS Phase Counter Period MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PHCNTPER[15] PHCNTPER[14] PHCNTPER[13] PHCNTPER[12] PHCNTPER[11] PHCNTPER[10] PHCNTPER[9] PHCNTPER[8] Default 0 0 0 0 0 0 0 0
PHCNTPER[15:0]: The Phase Counter Period (PHCNTPER15:0]) bits are used to program the Phase Counter period of the Phase Detector. These bits are used to set the end of count of the Phase Counter. The Phase Counter is reset on the next clock cycle following the detection of its end of count. The Phase Counter count (Nphcnt) is equal to the PHCNTPER value plus 1. For the system to operate properly, Nphcnt need to be greater than 1023.
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Register 0xDD: WANS Phase Average Period Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Unused Unused Unused PHAVGPER[3] PHAVGPER[2] PHAVGPER[1] PHAVGPER[0] Default X X X X 0 0 0 0
PHAVGPER[3:0]: The Phase Average Period (FRACQPER[3:0]) bits are used to set the number of consecutive valid Phase Samples accumulated to form the Phase Word. The number of samples is expressed as a power of 2, i.e.: Nfracq = 2FRACQPER
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Register 0xE0: RASE Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SDBERE: The SDBERE bit is the interrupt enable for the signal degrade threshold alarm. When SDBERE is a logic one, an interrupt is generated when the SD alarm is declared or removed. SFBERE: The SFBERE bit is the interrupt enable for the signal fail threshold alarm. When SFBERE is a logic one, an interrupt is generated when the SF alarm is declared or removed. Z1/S1E: The Z1/S1 interrupt enable is an interrupt mask for changes in the received synchronization status. When Z1/S1E is a logic one, an interrupt is generated when a new synchronization status message is extracted into the Receive Z1/S1 register. COAPSE: The COAPS interrupt enable is an interrupt mask for changes in the received APS code. When COAPSE is a logic one, an interrupt is generated when a new K1/K2 code value is extracted into the RASE Receive K1 and RASE Receive K2 registers. Type R/W R/W R/W R/W R/W Function PSBFE COAPSE Z1/S1E SFBERE SDBERE Unused Unused Unused Default 0 0 0 0 0 X X X
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PSBFE: The PSBF interrupt enable is an interrupt mask for protection switch byte failure alarms. When PSBFE is a logic one, an interrupt is generated when PSBF is declared or removed.
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Register 0xE1: RASE Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PSBFV: The PSBFV bit indicates the protection switching byte failure alarm state. The alarm is declared (PSBFV is set high) when twelve successive frames have been received without three consecutive frames containing identical K1 bytes. The alarm is removed (PSBFV is set low) when three consecutive frames containing identical K1 bytes have been received. SDBERV: The SDBERV bit indicates the signal degrade threshold crossing alarm state. The alarm is declared (SDBERV is set high) when the bit error rate exceeds the threshold programmed in the RASE SD Declaring Threshold registers. The alarm is removed (SDBERV is set low) when the bit error rate is below the threshold programmed in the RASE SD Clearing Threshold registers. SFBERV: The SFBERV bit indicates the signal failure threshold crossing alarm state. The alarm is declared (SFBERV is set high) when the bit error rate exceeds the threshold programmed in the RASE SF Declaring Threshold registers. The alarm is removed (SFBERV is set low) when the bit error rate is below the threshold programmed in the RASE SF Clearing Threshold registers. SDBERI: The SDBERI bit is set high when the signal degrade threshold crossing alarm is declared or removed. This bit is cleared when the RASE Interrupt Status register is read. Type R R R R R R R R Function PSBFI COAPSI Z1/S1I SFBERI SDBERI SFBERV SDBERV PSBFV Default X X X X X X X X
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SFBERI: The SFBERI bit is set high when the signal failure threshold crossing alarm is declared or removed. This bit is cleared when the RASE Interrupt Status register is read. Z1/S1I: The Z1/S1I bit is set high when a new synchronization status message has been extracted into the RASE Receive Z1/S1 register. This bit is cleared when the RASE Interrupt Status register is read. COAPSI: The COAPSI bit is set high when a new APS code value has been extracted into the RASE Receive K1 and RASE Receive K2 registers. This bit is cleared when the RASE Interrupt Status register is read. PSBFI: The PSBFI bit is set high when the protection switching byte failure alarm is declared or removed. This bit is cleared when the RASE Interrupt Status register is read.
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PMC-Sierra, Inc.
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Register 0xE2: RASE Configuration/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SDCMODE: The SDCMODE alarm bit selects the RASE window size to use for clearing the SD alarm. When SDCMODE is a logic zero, the RASE clears the SD alarm using the same window size used for declaration. When SDCMODE is a logic one, the RASE clears the SD alarm using a window size that is 8 times longer than the alarm declaration window size. The declaration window size is determined by the RASE SD Accumulation Period registers. SDSMODE: The SDSMODE bit selects the RASE saturation mode. When SDSMODE is a logic zero, the RASE limits the number of B2 errors accumulated in one frame period to the RASE SD Saturation Threshold register value. When SDSMODE is a logic one, the RASE limits the number of B2 errors accumulated in one window subtotal accumulation period to the RASE SD Saturation Threshold register value. Note that the number of frames in a window subtotal accumulation period is determined by the RASE SD Accumulation Period register value. SDBERTEN: The SDBERTEN bit selects automatic monitoring of line bit error rate threshold events by the RASE. When SDBERTEN is a logic one, the RASE continuously monitors line BIP errors over a period defined in the RASE configuration registers. When SDBERTEN is a logic zero, the RASE BIP accumulation logic is disabled, and the RASE logic is reset to the declaration monitoring state. Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z1/S1_CAP SFBERTEN SFSMODE SFCMODE SDBERTEN SDSMODE SDCMODE Reserved Default 0 0 0 0 0 0 0 0
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
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All RASE accumulation period and threshold registers should be set up before SDBERTEN is written. SFCMODE: The SFCMODE alarm bit selects the RASE window size to use for clearing the SF alarm. When SFCMODE is a logic zero, the RASE clears the SF alarm using the same window size used for declaration. When SFCMODE is a logic one, the RASE clears the SF alarm using a window size that is 8 times longer than the alarm declaration window size. The declaration window size is determined by the RASE SF Accumulation Period registers. SFSMODE: The SFSMODE bit selects the RASE saturation mode. When SFSMODE is a logic zero, the RASE limits the number of B2 errors accumulated in one frame period to the RASE SF Saturation Threshold register value. When SFSMODE is a logic one, the RASE limits the number of B2 errors accumulated in one window subtotal accumulation period to the RASE SF Saturation Threshold register value. Note that the number of frames in a window subtotal accumulation period is determined by the RASE SF Accumulation Period register value. SFBERTEN: The SFBERTEN bit enables automatic monitoring of line bit error rate threshold events by the RASE. When SFBERTEN is a logic one, the RASE continuously monitors line BIP errors over a period defined in the RASE configuration registers. When SFBERTEN is a logic zero, the RASE BIP accumulation logic is disabled, and the RASE logic is reset to the declaration monitoring state. All RASE accumulation period and threshold registers should be set up before SFBERTEN is written. Z1/S1_CAP: The Z1/S1_CAP bit enables the Z1/S1 Capture algorithm. When Z1/S1_CAP is a logic one, the Z1/S1 clock synchronization status message nibble must have the same value for eight consecutive frames before writing the new value into the RASE Receive Z1/S1 register. When Z1/S1_CAP is logic zero, the Z1/S1 nibble value is written directly into the RASE Receive Z1/S1 register. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
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Register 0xE3: RASE SF Accumulation Period LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SFSAP[7] SFSAP[6] SFSAP[5] SFSAP[4] SFSAP[3] SFSAP[2] SFSAP[1] SFSAP[0] Default 0 0 0 0 0 0 0 0
Register 0xE4: RASE SF Accumulation Period Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SFSAP[15] SFSAP[14] SFSAP[13] SFSAP[12] SFSAP[11] SFSAP[10] SFSAP[9] SFSAP[8] Default 0 0 0 0 0 0 0 0
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Register 0xE5: RASE SF Accumulation Period MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SFSAP[23:0]: The SFSAP[23:0] bits represent the number of 8 KHz frames used to accumulate the B2 error subtotal. The total evaluation window to declare the SF alarm is broken into 8 subtotals, so this register value represents 1/8 of the total sliding window size. Refer to the Operation section for recommended settings. Type R/W R/W R/W R/W R/W R/W R/W R/W Function SFSAP[23] SFSAP[22] SFSAP[21] SFSAP[20] SFSAP[19] SFSAP[18] SFSAP[17] SFSAP[16] Default 0 0 0 0 0 0 0 0
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Register 0xE6: RASE SF Saturation Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SFSTH[7] SFSTH[6] SFSTH[5] SFSTH[4] SFSTH[3] SFSTH[2] SFSTH[1] SFSTH[0] Default 0 0 0 0 0 0 0 0
Register 0xE7: RASE SF Saturation Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SFSTH[11:0]: The SFSTH[11:0] value represents the allowable number of B2 errors that can be accumulated during an evaluation window before an SF threshold event is declared. Setting this threshold to 0xFFF disables the saturation functionality. Refer to the Operation section for the recommended settings. R/W R/W R/W R/W Type Function Unused Unused Unused Unused SFSTH[11] SFSTH[10] SFSTH[9] SFSTH[8] Default X X X X 0 0 0 0
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Register 0xE8: RASE SF Declaring Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SFDTH[7] SFDTH[6] SFDTH[5] SFDTH[4] SFDTH[3] SFDTH[2] SFDTH[1] SFDTH[0] Default 0 0 0 0 0 0 0 0
Register 0xE9: RASE SF Declaring Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SFDTH[11:0]: The SFDTH[11:0] value determines the threshold for the declaration of the SF alarm. The SF alarm is declared when the number of B2 errors accumulated during an evaluation window is greater than or equal to the SFDTH[11:0] value. Refer to the Operation section for the recommended settings. R/W R/W R/W R/W Type Function Unused Unused Unused Unused SFDTH[11] SFDTH[10] SFDTH[9] SFDTH[8] Default X X X X 0 0 0 0
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Register 0xEA: RASE SF Clearing Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SFCTH[7] SFCTH[6] SFCTH[5] SFCTH[4] SFCTH[3] SFCTH[2] SFCTH[1] SFCTH[0] Default 0 0 0 0 0 0 0 0
Register 0xEB: RASE SF Clearing Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SFCTH[11:0]: The SFCTH[11:0] value determines the threshold for the removal of the SF alarm. The SF alarm is removed when the number of B2 errors accumulated during an evaluation window is less than the SFCTH[11:0] value. Refer to the Operation section for the recommended settings. R/W R/W R/W R/W Type Function Unused Unused Unused Unused SFCTH[11] SFCTH[10] SFCTH[9] SFCTH[8] Default X X X X 0 0 0 0
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Register 0xEC: RASE SD Accumulation Period LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SDSAP[7] SDSAP[6] SDSAP[5] SDSAP[4] SDSAP[3] SDSAP[2] SDSAP[1] SDSAP[0] Default 0 0 0 0 0 0 0 0
Register 0xED: RASE SD Accumulation Period Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SDSAP[15] SDSAP[14] SDSAP[13] SDSAP[12] SDSAP[11] SDSAP[10] SDSAP[9] SDSAP[8] Default 0 0 0 0 0 0 0 0
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0xEE: RASE SD Accumulation Period MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SDSAP[23] SDSAP[22] SDSAP[21] SDSAP[20] SDSAP[19] SDSAP[18] SDSAP[17] SDSAP[16] Default 0 0 0 0 0 0 0 0
SDSAP[23:0]: The SDSAP[23:0] bits represent the number of 8 KHz frames used to accumulate the B2 error subtotal. The total evaluation window to declare the SD alarm is broken into 8 subtotals, so this register value represents 1/8 of the total sliding window size. Refer to the Operation section for recommended settings.
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SATURN USER NETWORK INTERFACE (622-POS)
Register 0xEF: RASE SD Saturation Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SDSTH[7] SDSTH[6] SDSTH[5] SDSTH[4] SDSTH[3] SDSTH[2] SDSTH[1] SDSTH[0] Default 0 0 0 0 0 0 0 0
Register 0xF0: RASE SD Saturation Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SDSTH[11:0]: The SDSTH[11:0] value represents the allowable number of B2 errors that can be accumulated during an evaluation window before an SD threshold event is declared. Setting this threshold to 0xFFF disables the saturation functionality. Refer to the Operation section for the recommended settings. R/W R/W R/W R/W Type Function Unused Unused Unused Unused SDSTH[11] SDSTH[10] SDSTH[9] SDSTH[8] Default X X X X 0 0 0 0
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Register 0xF1: RASE SD Declaring Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SDDTH[7] SDDTH[6] SDDTH[5] SDDTH[4] SDDTH[3] SDDTH[2] SDDTH[1] SDDTH[0] Default 0 0 0 0 0 0 0 0
Register 0xF2: RASE SD Declaring Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Unused Unused Unused SDDTH[11] SDDTH[10] SDDTH[9] SDDTH[8] Default X X X X 0 0 0 0
SDDTH[11:0]: The SDDTH[11:0] value determines the threshold for the declaration of the SD alarm. The SD alarm is declared when the number of B2 errors accumulated during an evaluation window is greater than or equal to the SDDTH[11:0] value. Refer to the Operation section for the recommended settings.
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SATURN USER NETWORK INTERFACE (622-POS)
Register 0xF3: RASE SD Clearing Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SDCTH[7] SDCTH[6] SDCTH[5] SDCTH[4] SDCTH[3] SDCTH[2] SDCTH[1] SDCTH[0] Default 0 0 0 0 0 0 0 0
Register 0xF4: RASE SD Clearing Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Unused Unused Unused SDCTH[11] SDCTH[10] SDCTH[9] SDCTH[8] Default X X X X 0 0 0 0
SDCTH[11:0]: The SDCTH[11:0] value determines the threshold for the removal of the SD alarm. The SD alarm is removed when the number of B2 errors accumulated during an evaluation window is less than the SDCTH[11:0] value. Refer to the Operation section for the recommended settings.
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0xF5: RASE Receive K1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K1[7:0]: The K1[7:0] bits contain the current K1 code value. The contents of this register are updated when a new K1 code value (different from the current K1 code value) has been received for three consecutive frames. An interrupt may be generated when a new code value is received (using the COAPSE bit in the RASE Interrupt Enable Register). K1[7] is the most significant bit corresponding to bit 1, the first bit received. K1[0] is the least significant bit, corresponding to bit 8, the last bit received. Type R R R R R R R R Function K1[7] K1[6] K1[5] K1[4] K1[3] K1[2] K1[1] K1[0] Default X X X X X X X X
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0xF6: RASE Receive K2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K2[7:0]: The K2[7:0] bits contain the current K2 code value. The contents of this register are updated when a new K2 code value (different from the current K2 code value) has been received for three consecutive frames. An interrupt may be generated when a new code value is received (using the COAPSE bit in the RASE Interrupt Enable Register). K2[7] is the most significant bit corresponding to bit 1, the first bit received. K2[0] is the least significant bit, corresponding to bit 8, the last bit received. Type R R R R R R R R Function K2[7] K2[6] K2[5] K2[4] K2[3] K2[2] K2[1] K2[0] Default X X X X X X X X
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0xF7: RASE Receive Z1/S1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z1/S1[3:0]: The lower nibble of the first Z1/S1 byte contained in the receive stream is extracted into this register. The Z1/S1 byte is used to carry synchronization status messages between line terminating network elements. Z1/S1[3] is the most significant bit corresponding to bit 5, the first bit received. Z1/S1[0] is the least significant bit, corresponding to bit 8, the last bit received. An interrupt may be generated when a byte value is received that differs from the value extracted in the previous frame (using the Z1/S1E bit in the RASE Interrupt Enable Register). In addition, debouncing can be performed where the register is not loaded until eight of the same consecutive nibbles are received. Debouncing is controlled using the Z1/S1_CAP bit in the RASE Configuration/Control register. Z1/S1[7:4]: The upper nibble of the first Z1/S1 byte contained in the receive stream is extracted into this register. No interrupt is asserted on the change of this nibble. In addition, when the Z1/S1_CAP bit in the RASE Configuration/Control register selects debouncing, the upper nibble is only updated when eight of the same consecutive lower nibbles are received. Type R R R R R R R R Function Z1/S1[7] Z1/S1[6] Z1/S1[5] Z1/S1[4] Z1/S1[3] Z1/S1[2] Z1/S1[1] Z1/S1[0] Default X X X X X X X X
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0xFC: S/UNI-622-POS Concatenation Status and Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOPCE: The LOPCE bit is the interrupt enable for the Loss of Pointer Concatenation event. When LOPCE is a logic one, an interrupt is generated when the state of the Loss of Pointer Concatenation indicator changes. AISCE: The AISCE bit is the interrupt enable for the Pointer AIS event. When AISCE is a logic one, an interrupt is generated when the state of the Pointer AIS indicator changes. LOPCV: The LOPCV bit is the Loss of Pointer Concatenation indicator. When LOPCV is logic one, the STS-12c/STM-4-4c pointers do not indicate a concatenated payload. When LOPCV and AISCV are both logic zero, a STS-12c/STM-4-4c payload is indicated. AISCV: The ASICV bit is the Pointer AIS indicator. When AISCV is logic one, the STS-12c/STM-4-4c pointer indicates a pointer AIS condition. When LOPC and AISCV are both logic zero, a STS-12c/STM-4-4c payload is indicated. R/W R/W R R Type Function Unused Unused AISCV LOPCV Unused Unused AISCE LOPCE Default X X X X X X 0 0
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PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0xFD: S/UNI-622-POS Concatenation Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOPCI: A logic one on the LOPCI bit indicates that a transition has occurred on the Loss of Pointer Concatenation indicator. This bit is cleared when this register is read. AISCI: A logic one on the AISCI bit indicates that a transition has occurred on the Pointer AIS indicator. This bit is cleared when this register is read. R R Type Function Unused Unused Unused Unused Unused Unused AISCI LOPCI Default X X X X X X X X
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PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
12 TEST FEATURES DESCRIPTION Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the S/UNI-622-POS. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[8]) is high. In addition, the S/UNI-622-POS also supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port for use in board testing. All digital device inputs may be read and all digital device outputs may be forced via the JTAG test port. Table 10: Test Mode Register Memory Map
Address 0x000-0x0FF 0x100 0x101-0x1FF Register Normal Mode Registers Master Test Register
Reserved For Production Test
12.1 Master Test and Test Configuration Registers Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x100: Master Test Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W R/W W W W W Type Function Unused Reserved PMCATST PMCTST DBCTRL Reserved HIZDATA HIZIO Default X X X X X 0 X 0
This register is used to enable S/UNI-622-POS test features. All bits, except PMCTST, PMCATST and BYPASS are reset to zero by a reset of the S/UNI-622POS using either the RSTB input or the Master Reset register. PMCTST and BYPASS are reset when CSB is high. PMCTST, PMCATST and BYPASS can also be reset by writing a logic zero to the corresponding register bit. HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-622POS . While the HIZIO bit is a logic one, all output pins of the S/UNI-622POS except the data bus and output TDO are held tri-state. The microprocessor interface is still active. While the HIZDATA bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL bit. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic one and PMCTST is set to logic one, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-622-POS to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads.
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SATURN USER NETWORK INTERFACE (622-POS)
PMCTST: The PMCTST bit is used to configure the S/UNI-622-POS for PMC's manufacturing tests. When PMCTST is set to logic one, the S/UNI-622-POS microprocessor port becomes the test access port used to run the PMC "canned" manufacturing test vectors. The PMCTST bit can be cleared by setting CSB to logic one and RSTB to logic zero or by writing logic zero to the bit. PMCATST: The PMCATST bit is used to configure the analog portion of the S/UNI-622POS for PMC's manufacturing tests. The PMCTST bit can be cleared by setting CSB to logic one and RSTB to logic zero or by writing logic zero to the bit.
Reserved: The reserved bit must be programmed to logic one for proper operation
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12.2 JTAG Test Port The JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operation section. Table 11: Instruction Register (Length - 3 bits) Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Table 12: S/UNI-622-POS Identification Register Length Version Number Part Number Manufacturer's Identification Code Device Identification 32 bits 2H 5357H 0CDH 053570CDH
Table 13: S/UNI-622-POS Boundary Scan Register
Pin/Enable RSTB ALE CSB RDB WRB A[8] A[7] A[6] A[5] Register Bit 134 133 132 131 130 129 128 127 126 Cell Type IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL Device I.D. 0 0 0 0 0 1 0 1 0
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Pin/Enable A[4] A[3] A[2] A[1] A[0] TFPI TLD TSD Tied to Logic `0' LIFSEL PECLV RBYP TERR TEOP TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TMOD TPRTY TSOC/TSOP TENB TCA/TPA TFCLK REON RFCLK RENB RERR RVAL
Register Bit 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
Cell Type IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IN_CELL OUT_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL
Device I.D. 0 1 1 0 1 0 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 -
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Pin/Enable RCA/RPA RSOC/RSOP REOP RPRTY RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RMOD RDAT[0] SYSSEL POS_ATMB RLD RLDCLK RSD RSDCLK RALRM RCLK RFPO OOF PICLK PIN[0] PIN[1] PIN[3] PIN[4] FPIN PIN[2] PIN[7] PIN[6] PTCLK
Register Bit 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
Cell Type OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
Device I.D. -
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Pin/Enable PIN[5] POUT[0] POUT[1] FPOUT POUT[5] POUT[4] POUT[3] POUT[2] POUT[6] POUT[7] INTB_OEN INTB D[7] D[7]_OEN D[6] D[6]_OEN D[5] D[5]_OEN D[4] D[4]_OEN D[3] D[3]_OEN D[2] D[2]_OEN D[1] D[1]_OEN D[0] D[0]_OEN APS[4] APS[4]_OEN APS[3] APS[3]_OEN APS[2] APS[2]_OEN APS[1] APS[1]_OEN APS[0] APS[0]_OEN TCLK TFPO TLDCLK
Register Bit 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Cell Type IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
Device I.D. -
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Pin/Enable TSDCLK HIZ TCK TMS TDI TDO TRSTB
Register Bit 2 1
Cell Type OUT_CELL OUT_CELL TAP Input TAP Input TAP Input TAP Output TAP Input
Device I.D. -
NOTES: 1. Enable "pinname_OEN" tristates pin "pinname" when set high. 2. ROEN is the active low output enable for RDAT[15:0], RSOC/RSOP, RVAL, RPRTY, REOP, RERR and RMOD. 3. HIZ is the active low output enable for all OUT_CELL types except D[7:0], RDAT[15:0], RSOC/RSOP, RVAL, RPRTY, REOP, RERR, RMOD, APS[4:0] and INTB. 4. RSTB is the first bit of the boundary scan chain closest to the TDI TAP input. 12.2.1 Boundary Scan Cells In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table located above.
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Figure 14: Input Observation Cell (IN_CELL)
IDCODE Scan Chain Out
Input Pad
G1 G2 SHIFT-DR
INPUT to internal logic
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
Figure 15: Output Cell (OUT_CELL)
Scan Chain Out EXTEST Output or Enable from system logic IDOODE SHIFT-DR
G1 1 G1 G2 12 1 2 MUX 12 12 D C D C 1
MUX
OUTPUT or Enable
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
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Figure 16: Bidirectional Cell (IO_CELL)
Scan Chain Out INPUT to internal logic
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin
G1 1 G1 G2 12 1 2 MUX 12 12 1
MUX
OUTPUT to pin
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
Figure 17: Layout of Output Enable and Bidirectional Cells
Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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13 OPERATION 13.1 SONET/SDH Frame Mappings and Overhead Byte Usage 13.1.1 ATM Mapping The S/UNI-622-POS processes the ATM cell mapping for STS-12c/STM-4-4c as shown below in Figure 18. The S/UNI-622-POS processes the transport and path overhead required to support ATM UNIs and NNIs. In addition, the S/UNI622-POS provides support for the APS bytes, the data communication channels and provides full control and observability of the transport and path overhead bytes through register access. In Figure 18, the STS-12c/STM-4-4c mapping is shown. In this mapping, three stuff columns are included in the SPE. No other options are provided. Figure 18: ATM Mapping into the STS-12c/STM-4-4c SPE
1080 Bytes Transport Overhea d Section Overhea d Pointer J1 B3 C2 G1 F2 Line Overhea d H4 00 00 00 S T U F F S T U F F S T U F F F I X E D F I X E D F I X E D ATM Cell 1044 Bytes
ATM Cell
9 Bytes
ATM Cell
13.1.2 Packet over SONET/SDH Mapping The S/UNI-622-POS processes the Packet over SONET/SDH mapping for STS12c/STM-4-4c as shown below in Figure 19. The S/UNI-622-POS processes the transport and path overhead required to support Packet over SONET/SDH applications. In addition, the S/UNI-622-POS provides support for the APS bytes, the data communication channels and provides full control and observability of the transport and path overhead bytes through register access. In Figure 19, the STS-12c/STM-4-4c mapping is shown. In this mapping, the entire SPE is used for POS Frames.
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Figure 19: POS Mapping into the STS-12c/STM-4-4c SPE
1080 Bytes Transport Overhea d Section Overhea d Pointer J1 B3 C2 G1 F2 Line Overhea d H4 00 00 00 S T U F F S T U F F S T U F F F I X E D F I X E D F I X E D POS Frame POS Frame 1044 Bytes
POS Frame
9 Bytes
POS Frame
13.1.3 Transport and Path Overhead Bytes Under normal operating conditions, the S/UNI-622-POS processes a subset of the complete transport overhead present in an STS-12c/STM-4-4c stream. The byte positions processed by the S/UNI-622-POS are indicated in Figure 20. Figure 20: STS-12c/STM-4-4c Overhead
STS-12c Transport Overhead STM-4 Section Overhead A1 B1 D1 H1 B2 D4 D7 D10 S1 Z1 Z1 H1 B2 H1 B2 H1 B2 H1 B2 H1 B2 H1 B2 H1 B2 H1 B2 H1 B2 H1 B2 H1 B2 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 E1 D2 H2 K1 D5 D8 D11 Z2 Z2 M1 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 F1 D3 H3 K2 D6 D9 D12 E2 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 Z0 Z0 Z0
Transport Overhead Bytes A1, A2: J0 The frame alignment bytes (A1, A2) locate the SONET/SDH frame in the STS-12c/STM-4-4c serial stream. The J0 byte is currently defined as the STS-12c/STM-4-4c section trace byte for SONET/SDH. J0 byte is not scrambled by the frame synchronous scrambler. The Z0 bytes are currently defined as the STS-12c/STM-4-4c section growth bytes for SONET/SDH. Z0 bytes are not scrambled by the frame synchronous scrambler. The section bit interleaved parity byte provides a section error monitoring function.
Z0:
B1:
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In the transmit direction, the S/UNI-622-POS calculates the B1 byte over all bits of the previous frame after scrambling. The calculated code is then placed in the current frame before scrambling. In the receive direction, the S/UNI-622-POS calculates the B1 code over the current frame and compares this calculation with the B1 byte received in the following frame. B1 errors are accumulated in an error event counter. D1 - D3: The section data communications channel provides a 192 kbit/s data communications channel for network element to network element communications. In the transmit direction, the section DCC byte is inserted from a dedicated 192 kbit/s input, TSD. In the receive direction, the section DCC is extracted on a dedicated 192 kbit/s output, RSD. H1, H2: The pointer value bytes locate the path overhead column in the SONET/SDH frame. In the transmit direction, the S/UNI-622-POS inserts a fixed pointer value, with a normal new data flag indication in the first H1-H2 pair. The concatenation indication is inserted in the remaining H1-H2 pairs (STS-12c/STM-4-4c). Pointer movements can be induced using the TPOP registers. In the receive direction, the pointer is interpreted to locate the SPE. The loss of pointer state is entered when a valid pointer cannot be found. Path AIS is detected when H1, H2 contain an all ones pattern. H3: The pointer action bytes contain synchronous payload envelope data when a negative stuff event occurs. The all zeros pattern is inserted in the transmit direction. This byte is ignored in the receive direction unless a negative stuff event is detected. The line bit interleaved parity bytes provide a line error monitoring function. In the transmit direction, the S/UNI-622-POS calculates the B2 values. The calculated code is then placed in the next frame.
B2:
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In the receive direction, the S/UNI-622-POS calculates the B2 code over the current frame and compares this calculation with the B2 code receive in the following frame. Receive B2 errors are accumulated in an error event counter. K1, K2: The K1 and K2 bytes provide the automatic protection switching channel. The K2 byte is also used to identify line layer maintenance signals. Line RDI is indicated when bits 6, 7, and 8 of the K2 byte are set to the pattern '110'. Line AIS is indicated when bits 6, 7, and 8 of the K2 byte are set to the pattern '111'. In the transmit direction, the S/UNI-622-POS provides register control for the K1 and K2 bytes. In the receive direction, the S/UNI-622-POS provides register access to the filtered APS channel. Protection switch byte failure alarm detection is provided. The K2 byte is examined to determine the presence of the line AIS, or the line RDI maintenance signals D4 - D12: The line data communications channel provides a 576 kbit/s data communications channel for network element to network element communications. In the transmit direction, the line DCC byte is inserted from a dedicated 576 kbit/s input, TLD. In the receive direction, the line DCC is extracted on a dedicated 576 kbit/s output, RLD. S1: The S1 byte provides the synchronization status byte. Bits 5 through 8 of the synchronization status byte identifies the synchronization source of the STS-12c/STM-4-4c signal. Bits 1 through 4 are currently undefined. In the transmit direction, the S/UNI-622-POS provides register control for the synchronization status byte. In the receive direction, the S/UNI-622-POS provides register access to the synchronization status byte. The SSTB block also provides circuitry to detect synchronization status mismatch and unstable alarms. Z1: The Z1 bytes are located in the second and third STS-1's locations of an STS-12c/STM-4-4c and are allocated for future growth.
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M1:
The M1 byte is located in the third STS-1 locations of a STS12c/STM-4-4c and provides a line far end block error function for remote performance monitoring. The Z2 bytes are located in the first and second STS-1's locations of a STS-12c/STM-4-4c and are allocated for future growth. In the transmit direction, Z2 byte is internally generated. The number of B2 errors detected in the previous interval is inserted. In the receive direction, a legal Z2 byte value is added to the line FEBE event counter.
Z2:
Path Overhead Bytes J1: The Path Trace byte is used to repetitively transmit a 64-byte CLLI message (for SONET/SDH networks), or a 16-byte E.164 address (for SDH networks). When not used, this byte should be set to transmit continuous null characters. Null is defined as the ASCII code, 0x00. In the transmit direction, characters can be inserted using the TPOP Path Trace register or the SPTB block. The register is the default selection and resets to 0x00 to enable the transmission of NULL characters from a reset state. In the receive direction, the path trace message is optionally extracted into the 16 or 64 byte path trace message buffer. B3: The path bit interleaved parity byte provides a path error monitoring function. In the transmit direction, the S/UNI-622-POS calculates the B3 bytes. The calculated code is then placed in the next frame. In the receive direction, the S/UNI-622-POS calculates the B3 code and compares this calculation with the B3 byte received in the next frame. B3 errors are accumulated in an error event counter. C2: The path signal label indicator identifies the equipped payload type. For ATM payloads, the identification code is 0x13. For Packet over SONET/SDH (including X43+1 payload scrambling), the identification code is 0x16.
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In the transmit direction, the S/UNI-622-POS inserts the value 0x13 or 0x16 using the TPOP Path Signal Label register. In the receive direction, the code is available in the RPOP Path Signal Label register. In addition, the SPTB block also provides circuitry to detect path signal label mismatch and unstable alarms. G1: The path status byte provides a path FEBE function, and a path remote defect indication function. Three bits are allocated for remote defect indications: bit 5 (the path RDI bit), bit 6 (the auxiliary path RDI bit) and bit 7 (Enhanced RDI bit). Taken together these bits provide a eight state path RDI code that can be used to categorize path defect indications. In the transmit direction, the S/UNI-622-POS provides register bits to control the path RDI (bit 5) and auxiliary path RDI (bit 6) states. For path FEBE, the number of B3 errors detected in the previous interval is inserted either automatically or using a register. This path FEBE code has 9 legal values, namely 0 to 8 errors. In the receive direction, a legal path FEBE value is accumulated in the path FEBE event counter. In addition, the path RDI and auxiliary path RDI signal states are available in internal registers. H4: The multi-frame indicator byte is a payload specific byte, and is not used for ATM payloads. This byte is forced to 0x00 in the transmit direction, and is ignored in the receive direction. The path growth bytes provide three unused bytes for future use. In the transmit direction, the growth bytes may be inserted from the three TPOP Path Growth byte registers.
Z3 - Z5:
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13.2 ATM Cell Data Structure ATM cells may be passed to/from the S/UNI-622-POS using a 27 word, 16-bit UTOPIA level 2 compliant data structure or using a 54 byte, 8-bit UTOPIA level 3 compliant data structure. The former data structure is shown in Figure 21 and described below. Figure 21: 16-bit Wide, 27 Word ATM Cell Structure
Bit 15 Bit 8 Bit 7 Bit 0
Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 Word 8
H1 H3 H5 Payload 1 Payload 3 Payload 5 Payload 7 Payload 9
H2 H4 HCS Status/Control Payload 2 Payload 4 Payload 6 Payload 8 Payload 10
Word 27
Payload 47
Payload 48
Bit 15 of each word is the most significant bit (which corresponds to the first bit transmitted or received). The header check sequence octet (HCS) is passed through this structure. The start of cell indication input and output (TSOC and RSOC) are coincident with Word 1 (containing the first two header octets). Word 3 of this structure contains the HCS octet in bits 15 to 8. In the receive direction, the lower 8 bits of Word 3 contain the HCS status octet. An all-zeros pattern in these 8 bits indicates that the associated header is error free. An all-ones pattern indicates that the header contains an uncorrectable error (if the HCSPASS bit in the RXCP Control Register is set to logic zero, the all-ones pattern will never be passed in this structure). An alternating ones and zeros pattern (0xAA) indicates that the header contained a correctable error. In this case the header passed through the structure is the "corrected" header.
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In the transmit direction, the HCS bit in the TXCP Control register determines whether the HCS is calculated internally or is inserted directly from the upper 8 bits of Word 3. The lower 8 bits of Word 3 contain the HCS control octet. The HCS control octet is an error mask that allows the insertion of one or more errors in the HCS octet. A logic one in a given bit position causes the inversion of the corresponding HCS bit position (for example a logic one in bit 7 causes the most significant bit of the HCS to be inverted). The HDCL control octet may be disabled by setting the HCSCTLEB register in the TXCP. ATM cells can also be passed to/from the S/UNI-622-POS using a 54 byte, 8-bit UTOPIA level 3 compliant data structure shown in Figure 22. Figure 22: 8-bit Wide, 54 Byte ATM Cell Structure
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 H1 H2 H3 H4 H5
Byte 6 HCS Status/Control Byte 7 Byte 8 Byte 9 Payload 1 Payload 2 Payload 3
Byte 54
Payload 48
Bit 7 of each byte is the most significant bit (which corresponds to the first bit transmitted or received). The header check sequence octet (HCS) is passed through this structure. The start of cell indication input and output (TSOC and RSOC) are coincident with Byte 1. 13.3 Packet over SONET/SDH Data Structure Packets may be written into the TXFP FIFO and read from the RXFP FIFO using either a 16-bit POS-PHY Level 2 or an 8-bt POS-PHY Level 3 defined data structure.
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The 16-bit POS-PHY Level 2 data structure is shown in Figure 23. The packet length of 63 bytes is chosen arbitrarily for illustrative purposes only. Other lengths are acceptable. Octets are written in the same order they are to be transmitted or they were received on the SONET/SDH line. Within an octet, the MSB (bit 7) is the first bit to be transmitted. All words are composed of two octets, except the last word of a packet which can have one or two bytes. If the TXFP is configured to not insert the FCS field, then these bytes should be included at the end of the packet. Similarly, if the RXFP is configured to not strip the FCS field, then these bytes will be included at the end of the packet. Figure 23: A 63 Byte Packet Data Structure
Bit 15 Bit 8 Bit 7 Bit 0
Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Byte 1 Byte 3 Byte 5 Byte 7 Byte 9 Byte 11 Byte 13
Byte 2 Byte 4 Byte 6 Byte 8 Byte 10 Byte 12 Byte 14
Word 32
Byte 63 A 63 Byte Frame
XX
The 8-bit POS-PHY Level 3 data structure is shown in Figure 24. The packet length of 63 bytes is chosen arbitrarily for illustrative purposes only. Other lengths are acceptable. However, on the transmit interface, packets with an odd number of bytes must be transferred with a one clock pause (TENB high). Octets are written in the same order they are to be transmitted or they were received on the SONET/SDH line. Within an octet, the MSB (bit 7) is the first bit to be transmitted. If the TXFP does not insert the FCS field, then these bytes should be included at the end of the packet. If the RXFP does not strip the FCS field, then these bytes will be included at the end of the packet.
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Figure 24: A 63 Byte Packet Data Structure
Byte 1 Byte 2 Byte 3 Byte 4
Byte 63 A 63 Byte Frame
Both the start of the packet and the end of the packet must be identified by the TSOP/RSOP and TEOP/REOP signals. When the first section of a packet is transferred over the interface, the TSOP/RSOP signals will be high for Byte 1 of the packet only. 13.4 Setting ATM Mode of Operation The following sequence of operation should be used to prepare the device for the ATM operation. 1- Input pin POS_ATMB (Y21) should be tied low to enable ATM operation. This pin can be overridden in software by writing a logic one to the RMOVR bit (Register 0x90) and TMOVR bit (Register 0x92). Writing a logic zero to the RPOS_ATMB bit (Register 0x90) and the TPOS_ATMB bit (Register 0x92) can then be used to enable ATM operation. When using the software override feature, these bits must be set after step (2), as resetting the device restores the registers to their default values. This feature is useful for building a single PHY card that can be configured in software as a POS or ATM card. 2- Reset the device. This can be done by asserting the RSTB pin or setting the RESET bit in the Master Reset and ID Register (Register 0x00).
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3- If the TFCLK, RFCLK and/or the PTCLK (if used) clock inputs are not stable clocks, wait until these clock inputs stabilize. Reset the DLL units associated with each clock input (write 0x00 to Registers 0x96, 0x9A and 0x9E respectively). 4- Reset the receive and transmit FIFO's by setting the FIFORST register bit in the TXCP (Register 0x80) and RXCP (Register 0x62) blocks. Keep this bit set for at least 1 s, then set the bit back to its inactive logic zero value. 5- Set the path signal label C2 byte (offset 0x054 and 0x048) to 0x13 to identify ATM payload data. 6- Reset the performance monitoring counters in TXCP and RXCP blocks by writing a logic zero to the Master Reset and Identity register (Register 0x00). TIP remains high as the performance monitoring registers are loaded, and is set to a logic zero when the transfer is complete. 13.5 Setting Packet-Over-SONET/SDH Mode of Operation The following sequence of operation should be used to prepare the device for the Packet over SONET/SDH (POS) operation. 1- Input pin POS_ATMB (Y21) should be tied high to enable POS operation. This pin can be overridden in software by writing a logic one to the RMOVR bit (Register 0x90) and TMOVR bit (Register 0x92). Writing a logic one to the RPOS_ATMB bit (Register 0x90) and the TPOS_ATMB bit (Register 0x92) can then be used to enable POS operation. When using the software override feature, these bits must be set after step (2), as resetting the device restores the registers to their default values. This feature is useful for building a single PHY card that can be configured in software as a POS or ATM card. 2- Reset the device. This can be done by asserting the RSTB pin or setting the RESET bit in the Master Reset and ID Register (Register 0x00). 3- If the TFCLK, RFCLK and/or the PTCLK (if used) clock inputs are not stable clocks, wait until these clock inputs stabilize. Reset the DLL units associated with each clock input (write 0x00 to Registers 0x96, 0x9A and 0x9E respectively).
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4- Reset the receive and transmit FIFO's by setting the FIFORST register bit in the TXFP (Register 0xC1) and RXFP (Register 0xA0) blocks. Keep this bit set for at least 1 s, then set the bit back to its inactive logic zero value. 5- Set the path signal label C2 byte (offset 0x054 and 0x048) to 0x16 to identify POS payload data. 6- Reset the performance monitoring counters in TXFP and RXFP blocks by writing a logic zero to the Master Reset and Identity register (Register 0x00). TIP remains high as the performance monitoring registers are loaded, and is set to a logic zero when the transfer is complete. 13.6 Setting SONET or SDH Mode of Operation The SONET and SDH standard for optical networking are very similar with only minor difference in overhead processing. The main difference between the SONET (Bellcore GR-253-CORE) and SDH (ITU.707) standards lies in the handling of some of the overhead bytes. Other details, like framing and data payload mappings are equivalent in SONET and SDH. The bit error rate (BER) monitoring requirements are also slightly different between SONET and SDH. An application note, PMC-950820, explains the different parameters in detail for the RASE block. The list below shows the various register setting to configure the S/UNI-16x155 for either SONET or SDH operation. Table 14: Settings for SONET or SDH Operation Configuration Registers SDH_J0/Z0 (register offset 0x004) ENSS (register offset 0x03D) Path LEN16 (register offset 0x028) Section LEN16 (register offset 0x050) S[1:0] (register offset 0x46) SONET 0 0 0 0 00 SDH X 1 1 1 10
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Notes: 1. SONET requires Z0 bytes to be set to the number corresponding to the STS-1 column number. SDH considers those bytes reserved. 2. When forcing a constant Z0 pattern (SDH_J0/ZO is high), the Z0 bytes must be DC balanced (approximately the same number of ones and zeros) as the bytes are not scrambled. Failure to do so may cause downstream clock recovery to lose lock. 3. SONET uses 64 byte trace messages while SDH uses 16 byte trace messages. 4. SDH specification requires the detector of SS bits to be "10". 5. The SS bits are undefined for SONET, but must be set to "10" for SDH. 13.7 Bit Error Rate Monitor The S/UN-622-POS provides two BERM blocks. One can be dedicated to monitor at the Signal Degrade (SD) error rate and the other dedicated to monitor at the Signal Fail (SF) error rate. The Bit Error Rate Monitor (BERM) block counts and monitors line BIP errors over programmable periods of time (window size). It can monitor to declare an alarm or to clear it if the alarm is already set. A different threshold and accumulation period must be used to declare or clear the alarm, whether or not those two operations are not performed at the same BER. The following table lists the recommended content of the BERM registers for different error rates (BER). Both BERMs in the TSB are equivalent and are programmed similarly. In a normal application they will be set to monitor different BER. When the SF/SD CMODE bit is set to one, the clearing monitoring is recommended to be performed using a window size that is 8 times longer than the declaration window size. When the SF/SD CMODE bit is set to zero, the clearing monitoring is recommended to be performed using a window size equal to the declaration window size. In all cases the clearing threshold is calculated for a BER that is 10 times lower than the declaration BER, as required in the references. The table indicates the declare BER and evaluation period only. The saturation threshold is not listed in the table, and should be programmed with the value 0xFFF by default, deactivating saturation. Saturation capabilities are provided to allow the user to address issues associated with error bursts. For additional information, please refer to the BERM application note (PMC950820) for more detailed information.
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Table 15: Recommended BERM settings
STS STS-12c STS-12c STS-12c STS-12c STS-12c STS-12c STS-12c STS-3c STS-3c STS-3c STS-3c STS-3c STS-3c STS-3c Declare BER 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-3 10-4 10-5 10-6 10-7 10-8 10-9 Evals / Second SF/SD SMODE 0 0 0 0 SF/SD CMODE SF/SD SAP 0x000008 0x000008 0x000019 0x0000FA 0x0009C4 0x005208 0x028C58 0x000008 0x00000D 0x000064 0x0003E8 0x002710 0x014438 0x0A2D78 SF/SD DTH 0x956 0x1A5 0x084 0x085 0x085 0x06E 0x056 0x245 0x0A3 0x084 0x085 0x085 0x06D 0x055 SF/SD CTH 0x1E9 0x03D 0x08E 0x08E 0x08E 0x079 0x062 0x083 0x0B4 0x08E 0x08E 0x08E 0x077 0x061
0.008
0.008 0.025 0.250 2.500 21.000 167.000
0
0 1 1 1 1 1 0 1 1 1 1 1 1
0
0 0 0 0 0 0
0.008
0.013 0.100 1.000 10.000 83.000 667.000
0
0 0
13.8 Auto Alarm Control Configuration The S/UNI-622-POS supports the automatic generation of transmit alarm information based on the detected receive alarms. This functionality is controlled by the master AUTOxx register bits in register 0x02 and the Auto Path and Line Configuration registers 0x08 to 0x0F. When consequential action is enabled for a given alarm condition, other S/UNI622-POS configuration registers become important. For instance, if consequential action for signal degrade is enabled, the RASE must be configured for the desired alarm thresholds. The following table lists register settings for path RDI and extended path RDI interfaces. Table 16: Path RDI and Extended RDI Register Settings Register 0x09 0x0A RDI 11111111 Xxxxxxxx EPRDI 01101111 11111111
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0x0B 0x40 13.9 Clocking Options
10xxx010 x00x00xx
11xxx111 x11x00xx
The S/UNI-622-POS supports several clocking modes. Figure 25 is an abstraction of the clocking topology. The S/UNI-622-POS can operate in source time, internally loop timed and externally loop timed. Figure 25: Clocking Structure
SLLE TRANSMIT DATA TCLK
PISO-622 TXD
CSU-622
LOOPT/SLLE SDLE
REFCLK
CRU-622
WANS
RXD RRCLK
SIPO-622
RECEIVE DATA RCLK
Source timed operation is used for all public user network interfaces (UNIs) and for private UNIs and private network node interfaces (NNIs) that are not synchronized to the recovered clock. The transmit clock in a public UNI must conform to SONET/SDH Network Element (NE) requirements specified in Bellcore GR-253-CORE. These requirements include jitter generation, short term clock stability, phase transients during synchronization failure, and holdover. The 77.76 MHz clock source is
RBYP/SDLE
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typically a VCO (or temperature compensated VCXO) locked to a primary reference source for public UNI applications. The accuracy of this clock source should be within 20 ppm of 77.76 MHz to comply with the SONET/SDH network element free-run accuracy requirements. The S/UNI-622-POS WANS block can be used to implement the system timing reference. The transmit clock in a private UNI or a private NNI may be locked to an external reference or may free-run. The simplest implementation requires an oscillator free-running at 77.76 MHz. Source timed operation is selected by clearing the LOOPT bit of the Master Configuration register. REFCLK is multiplied by 8 to become the 622.08 MHz transmit clock. REFCLK must be jitter free. The source REFCLK is also internally used as the clock recovery reference during receive loss of transition conditions. Internally loop timed operation is used for private UNIs and private NNIs that require synchronization to the recovered clock. This mode is selected by setting the LOOPT bit of the Master Control register to logic one. Normally, the transmit clock is locked to the receive data. In the event of a loss of signal/transition condition, the transmit clock is synthesized from REFCLK. Externally loop timed operation makes use of the WAN Synchronization block capabilities. This mode can be achieved when LOOPT is set to logic zero. The timing loop is achieved at the system level, through a microprocessor, an external VCXO and back through the REFCLK input. This mode allows an S/UNI-622-POS to meet Bellcore wander transfer and holdover stability requirements. 13.10 WAN Synchronization (WANS Block) The WANS provides a means to implement a Stratum 3 or lower system timing reference with a minimum amount of external circuitry. The WANS implements a phase detector necessary to create a digital control PLL. A description of how to program and use the WANS feature will be made available in the S/UNI-622-POS reference design (PMC-981070). 13.11 Loopback Operation The S/UNI-622-POS supports five loopback functions: path loopback, line loopback, data diagnostic loopback, parallel diagnostic loopback and serial diagnostic loopback. Each channel's loopback modes operate independently.
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The loopback modes are activated by the PDLE, LLE, DLE, DPLE and SDLE bits contained in the S/UNI-622-POS Master Configuration registers. The line loopback, see Figure 26, connects the high speed receive data and clock to the high speed transmit data and clock, and can be used for line side investigations (including clock recovery and clock synthesis). While in this mode, the entire receive path is operating normally and cells can be received through the FIFO interface. The serial diagnostic loopback, see Figure 27, connects the high speed transmit data and clock to the high speed receive data and clock. While in this mode, the entire transmit path is operating normally and data is transmitted on the TXD+/outputs. The parallel diagnostic loopback, see Figure 28, connects the byte wide transmit data and clock to the byte wide receive data and clock. While in this mode, the entire transmit path is operating normally and data is transmitted on the TXD+/outputs. The path diagnostic loopback, see Figure 29, connects the transmit path processor TPOP output to the receive path processor RPOP. While in this mode, the entire transmit path is operating normally and data is transmitted on the TXD+/- outputs. The data diagnostic loopback, see Figure 30, connects the transmit POS/ATM processor TXFP/TXCP) to the corresponding receive POS/ATM processor (RXFP/RXCP). While in this mode, the transmit path does not operate normally and the data transmitted on the TXD+/- outputs is invalid.
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Figure 26: Line Loopback Mode
Section/ Line DCC Insert
JTAG Test Access Port Tx POS Frame Processor
Tx Line I/F
Tx Section O/H Processor
Tx Line O/H Processor
Tx Path O/H Processor Tx ATM Cell Processor
UTOPIA ATM/SATURN POS-PHY Level 2 UTOPIA ATM/SATURN POS-PHY Level 3 System Interface
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a a
Section Trace Buffer Path Trace Buffer WAN Synch. Rx Line I/F Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor Section/ Line DCC Extract Rx APS, Sync Status, BERM Section/ Line DCC Insert JTAG Test Access Port Tx Line I/F Tx Section O/H Processor Tx Line O/H Processor Tx Path O/H Processor
Rx ATM Cell Processor
Rx POS Frame Processor
Microprocessor Interface
Figure 27: Serial Diagnostic Loopback Mode
Tx POS Frame Processor
UTOPIA ATM/SATURN POS-PHY Level 2 UTOPIA ATM/SATURN POS-PHY Level 3 System Interface
Tx ATM Cell Processor
a a
Section Trace Buffer Path Trace Buffer WAN Synch. Rx Line I/F Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor Section/ Line DCC Extract Rx APS, Sync Status, BERM
Rx ATM Cell Processor
Rx POS Frame Processor
Microprocessor Interface
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Figure 28: Parallel Diagnostic Loopback Mode
Section/ Line DCC Insert
JTAG Test Access Port Tx POS Frame Processor
Tx Line I/F
Tx Section O/H Processor
Tx Line O/H Processor
Tx Path O/H Processor Tx ATM Cell Processor
UTOPIA ATM/SATURN POS-PHY Level 2 UTOPIA ATM/SATURN POS-PHY Level 3 System Interface
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Section Trace Buffer Path Trace Buffer WAN Synch. Rx Line I/F Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor Section/ Line DCC Extract Rx APS, Sync Status, BERM
Section/ Line DCC Insert JTAG Test Access Port Tx Line I/F Tx Section O/H Processor Tx Line O/H Processor Tx Path O/H Processor
Rx ATM Cell Processor
Rx POS Frame Processor
Microprocessor Interface
Figure 29: Path Diagnostic Loopback Mode
Tx POS Frame Processor
UTOPIA ATM/SATURN POS-PHY Level 2 UTOPIA ATM/SATURN POS-PHY Level 3 System Interface
Tx ATM Cell Processor
a a
Section Trace Buffer Path Trace Buffer WAN Synch. Rx Line I/F Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor Section/ Line DCC Extract Rx APS, Sync Status, BERM
Rx ATM Cell Processor
Rx POS Frame Processor
Microprocessor Interface
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Figure 30: Data Diagnostic Loopback Mode
Section/ Line DCC Insert
JTAG Test Access Port Tx POS Frame Processor
Tx Line I/F
Tx Section O/H Processor
Tx Line O/H Processor
Tx Path O/H Processor Tx ATM Cell Processor
UTOPIA ATM/SATURN POS-PHY Level 2 UTOPIA ATM/SATURN POS-PHY Level 3 System Interface
13.12 1+1 APS Support The S/UNI-622-POS has the ability to exchange transmit path data in order to implement a 1+1 APS interface. In order to use this capability, the serial line side interface must be used (1+1 APS support is not available in OC3 operation) as the parallel line side interface is used as the transmit path APS port. The diagram in Figure 31 shows how to connect two S/UNI-622-POS devices for 1+1 APS operation. The working device is the source of transmit path for both the working and the protection channels. The transmit path process TPOP as well as the TXCP and TXFP processors are unused in the protection device. The working device sends the transmit path data steam to the protection device using the parallel line interface pins. The protection device adds section and line overhead to the transmit path data stream using its TSOP and TLOP units. Thus, each channel has unique K1/K2 byte control and monitoring.
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Section Trace Buffer Path Trace Buffer WAN Synch. Rx Line I/F Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor Section/ Line DCC Extract Rx APS, Sync Status, BERM
Rx ATM Cell Processor
Rx POS Frame Processor
Microprocessor Interface
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Figure 31: 1+1 APS Architecture
CSU Reference REFCLK TLOP RLOP APSPD PIN[7:0] APSRDI, APSFEBE APS FIFO FPIN PICLK RPOP POUT[7:0] FPOUT TCLK RPOP APSRDI, APSFEBE APSPD REFCLK TLOP RLOP
TSOP RSOP
TSOP RSOP
TPOP
APSOE APS[4:0] APS[4:0]
TPOP
RXCP
TXCP
TXCP
RXCP
Protection Channel Device
Working Channel Device
A 4-byte FIFO is used to handle wander between the TCLK of the working device and the TCLK of the protection device. Both transmit clocks TCLK must be the same frequency in order for this FIFO to operate normally. Therefore, the clock synthesis units (CSU) of both device must have the same reference clock input REFCLK. The working and protection devices cannot operate in loop time as the frequency difference between the receive clock and the reference clock will cause the FIFO to underrun or overrun corrupting the protection transmit path. In order to perform loop-time operation, an external clocking source must be used (for instance, the WANS functionality). The APS FIFO must be reset after both CSU units lock to the reference clock in order to center the FIFO. This the APSRST bit must be toggled when the ROOLV in the CSPI-622 indicates a CSU has lost lock or after a system reset. The ASPI register will indicate when the FIFO has corrupted data due to an overrun or an underrun. The active channel is selected using the receive ATM and POS System Interface. Thus, if the protection device is active, the receive System Interface of the protection device is used. If the working device is active, the receive System
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Interface of the working device is used. In all cases, the transmit System Interface of the working device is used for the transmit data stream. In order for the S/UNI-622-POS to support path AUTORDI and AUTOPFEBE functions, the APS[4:0] pins are used to exchange alarm information from the protection device to the TPOP of the working device. Thus, when the protection device is active, the working device must be configured to use the receive path alarm information from the protection device. Table 17 shows the register configurations for both normal operation and protection operation for both devices. Table 17: 1+1 APS Register 0x06 Settings
Bit APSEN APSOE APSPD APSFEBE APSRDI Work Device (Normal) Protect Device (Normal) 1 1 1 X X
Work Device (Protection)
1 0 0 1 1
Protect Device (Protection) 1 1 1 X X
1 0 0 0 0
13.13 JTAG Support The S/UNI-622-POS supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below.
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Figure 32: Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs.
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13.13.1
TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below. Figure 33: TAP Controller Finite State Machine
TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 0 1 Exit1-IR 0 Pause-IR 1 0 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
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13.13.2
States
Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO. 13.13.3 Instructions
BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
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STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state. 13.14 Board Design Recommendations The noise environment and signal integrity are often the limiting factors in system performance. Therefore, the following board design guidelines must be followed in order to ensure proper operation: 1. Use a single plane for both digital and analog grounds. 2. Provide separate +3.3 volt analog and +3.3 volt digital supplies, but otherwise connect the supply voltages together at one point close to the connector where +3.3 volts is brought to the card. 3. VBIAS biasing supply must be driven at a higher potential than the expected maximum digital input level. For 3.3 volt designs where all digital inputs are 3.3 volt TTL levels, VBIAS may be set to 3.3 volts or greater. For designs with 5.0 volt TTL levels, VBIAS must be set to 5.0 volts. PBIAS biasing supplies operate similarly. For designs using optical modules with 3.3 volt PECL levels, the PBIAS pins may be set to 3.3 volts or greater. For designs using optical modules with 5.0 volt PECL levels, the PBIAS pins must be set to 5.0 volts. If the serial interface is not being used, the PBIAS pins may be set to 3.3 volts. See the section on interfacing to ECL and PECL devices for more details 4. Ferrite beads are not advisable in digital switching circuits because inductive spiking (di/dt noise) is introduced into the power rail. Simple RC filtering is the best approach provided care is taken to ensure the IR drop in the resistance does not lower the supply voltage below the recommended operating voltage. 5. High-frequency decoupling capacitors are recommended for each biasing pins (VBIAS, PBIAS and QAVD) as close to the package pin as possible. Separate decoupling is required to prevent the transmitter from coupling noise into the receiver and to prevent power supply transients from coupling into some internal reference circuitry. See the section on Power Supplies for more details.
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6. Low-pass filtering networks are recommended for analog power supplies as close to the package pin as possible. Separate decoupling is required to prevent the transmitter from coupling noise into the receiver and to prevent power supply transients from coupling into some internal reference circuitry. See the section on Power Supplies for more details. 7. The high speed serial streams (TXD+/-, RXD+/, and RRCLK+/-) must be routed with 50 ohm controlled impedance circuit board traces and must be terminated with a matched load. Normal TTL-type design rules are not recommended and will reduce the performance of the device. See the section on interfacing to ECL and PECL devices for more details. 8. PECL traces between the S/UNI-622-POS and optical modules should not exceed 4 cm for proper jitter operation. Please refer to the S/UNI-622-POS reference design (PMC-981070) for further recommendations 13.15 Power Supplies Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible to blow these ESD protection devices or trigger latch up. The recommended power supply sequencing follows: 1. The VBIAS supply must be equal to or greater than the VDD supply during power up. By placing a decoupled 1 kohm in series with VBIAS as shown in Figure 34, this restriction may be ignored. 2. The PBIAS supplies must be equal to or greater than the AVD supply during power up. By placing a decoupled 1 kohm in series with the PBIAS supply as shown in Figure 34, this restriction may be ignored. 3. The VDD supply must be applied before or at the same time as QAVD and AVD supplies (the voltage difference between any two pins must be less than 0.5 volts). 4. VDD and VBIAS supplies must be applied before digital input pins are driven or the current per pin limited to less than the maximum DC input current specification.
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5. AVD and PBIAS supplies must be applied before analog input pins are driven or the current per pin limited to less than the maximum DC input current specification. 6. The differential voltage between VDD and AVD must be less than 1.0 volts including peak to peak noise.. The differential voltage between VDD and QAVD must be less than 0.5 volts including peak to peak noise. Otherwise, digital noise on VDD will be coupled into the sensitive analog circuitry. 7. Power down the device in the reverse sequence. Use the above current limiting technique for the analog power supplies. Small offsets in VDD / AVD discharge times will not damage the device. Analog circuitry is particularly susceptible to noise and thus we recommend the following analog power filter scheme shown Figure 34 and Figure 35. Sensitive analog power pins require RC filter networks in order to meet SONET/SDH jitter specifications. Some recommended notes follows: 8. Place each 0.1uF capacitor as close to its associated power pin as possible as shown in Figure 35. 9. The 0.1uF capacitors are ceramic X7R or X5R. 10. The 10uF capacitors are 10V X5R ceramic, 1210 size, from Tayio-Yuden, LMK325BJ106MN (visit their web site at www.t-yuden.com). 11. The 10uF capacitors and resistors do not have to be very close to power pins as they are filtering the power supply and not decoupling it. 12. The two 10uF X5R capacitors on pin C4 can be replaced by one 22uF, 10V, X5R LMK432BJ226MM from Tayio Yuden. 13. All resistors shown are 1/10 watt. 14. All other power pins not mentioned do not need any extra filtering or decoupling. Please refer to the S/UNI-622-POS reference design (PMC-981070) for further recommendations.
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Figure 34: Power Supply Filtering and Decoupling
47 +3.3V Pin P1 Pin AC5 47uF Tantalum 10uF X5R 0.1uF
47 Pin C4
10uF X5R
10uF X5R
0.1uF
+3.3V 0.1uF (9 caps)
Pins F2, H3, K3, L3, U3, Y1, AA5, AA8, C7 One cap as close as possible to each of these analog pins.
150 Pin A3
10uF X5R
0.1uF
+3.3V 0.1uF (9 caps) Pin A4
Pins C21, M20, V20, AA21, D12, B2, M4, AB2, Y12 One cap as close as possible to each of these digital pins.
150
10uF X5R
0.1uF
150 Pin D2 Pin D3 10uF X5R 0.1uF
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Figure 35: Power Supply Component Layout
CSU-AVD2 Pin-A4, AVD29 CSU-AVD1 PinA3, AVD30
15
15
10 F
0.1F
10 F
0.1F 0.1F
0.1F
0.1F
0.1F
10F
15
CSU-AVD3 Pin-D2 & D3, AVD1
S/UNI-622-POS 31 by 31 mm
0.1F
CSU-AVD0 Pin-C4, AVD31
0.1F 0.1F 0.1F 0.1F 0.1F 10 F 0.1F
X7R +/-5% for Loop Filter name C0, C1 pins P2, P3
4.7
0.1F
10 F
10F
0.1F
47nF
CRU-AVD4 Pin-P1, AVD8
4.7
47F 7.3by 4.3mm
0.1F
0.1F
1K
0.1F 0.1F
0.1F
Vbias, Pbias pins
0.1F
0.1F 0.1F 0.1F
CRU-AVD5 Pin-AC5, AVD17
13.16 Interfacing to ECL or PECL Devices In normal operation, the S/UNI-622-POS performs clock and data recovery on the incoming serial stream. As an option, internal clock and data recovery may be bypassed by setting the RBYP pin high and use an externally recovered receive clock on the RRCLK+/- pins. In this mode RXD+/- is sampled on the rising edge of RRCLK+/-. For example, Hewlett Packard provides HFCT/HFBR5207 optical transceivers with clock and data recovery and HFCT/HFBR-5208 transceivers without clock and data recovery. The HFCT-5207 has a 2x9 pin out having one 9 pin row matching the pin out of the HFCT-5208 and another 9 pin
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row which provides extra signals for the recovered clock. By using a footprint that will fit both devices, either device may be used. Only a few passive components are required to convert the optical transceivers signals to ECL (or PECL) logic levels. Figure 36 and Figure 37 illustrate the recommended configurations for both types of ECL voltage levels. The PECLV pin must be set appropriately for the selected configuration. Each PECL input and output has an associated ESD biasing pin PBIAS[3:0]. These biasing pins should be biased at the proper level to ensure the internal ESD diode structure is not forward biased. This means for 3.3V volt ECL logic levels (PECLV set high), the PBIAS pins may be biased from 3.3 volts to 5.0 volts. For 5.0 volt ECL logic levels (PECLV set low), the PBIAS pins must be biased at 5.0 volts. The bias pins should be high-frequency decoupled to prevent noise from coupling through the ESD structures and affecting the high-speed signals. The 50 ohm control impedance traces must be less than 4 cm in length to reduce the effect of signal reflections between the optical module and the S/UNI-622POS. Vias should be avoided on the signal path between the optical module and the S/UNI-622-POS as they can affect the jitter performance of the interface. Vias may be used for the termination networks as the inductive effective of a via will not significantly affect the termination performance. Figure 36: Interfacing S/UNI-622-POS PECL Pins to 3.3V Devices
RD+ 150 RDOptical Module Interface
50=Trace Impedance 100 50=Trace Impedance 150
RXD+ RXDS/UNI Optical Interface
TD+
49.9
50=Trace Impedance 0.1uF 63.4 +3.3 volts 50=Trace Impedance
TXD+
TDSD
49.9
TXDSD
150
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Figure 37: Interfacing S/UNI-622-POS PECL Pins to 5.0V Devices
RD+ 330 RDOptical Module Interface
50=Trace Impedance 100 50=Trace Impedance 330
RXD+
RXDS/UNI Optical Interface
TD+
49.9
50=Trace Impedance 0.1uF +5.0 volts 63.4 50=Trace Impedance
TXD+
TDSD
49.9
TXDSD
330
When a PECL input is not being used, the positive differential input must be tied to analog power (AVD) and the negative differential input must be tied to analog ground (AVS). In all cases, the PECL inputs must be driven with a differential voltage (do not connect both pins to AVD or AVS). When the PECL output is not being used, the external reference resistor TDREF1 may be tied to analog power (AVD) and TDREF0 may be tied to analog group (AVS) to disable the PECL output. Both positive and negative differential outputs of the PECL output may be tied both to analog ground (AVS). Please refer to the S/UNI-622-POS reference design (PMC-981070) for further recommendations. 13.17 Clock Synthesis and Recovery The Clock Synthesizer unit (CSU) in the S/UNI-622-POS requires an external reference clock REFCLK to generate the 622 MHz transmit clock. The REFCLK input is a PECL input in order to reduce the amount of noise coupled into the CSU. In most cases, the reference clock must be generated and propagated using PECL logic in order for the CSU to meet SONET/SDH intrinsic jitter specifications.
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In general, the reference clock REFCLK is supplied by a crystal oscillator with PECL outputs. The oscillator must have at least -115dBc/Hz between 12 kHz and 5 MHz frequency offset in order for the CSU to meet SONET/SDH intrinsic jitter specifications. Do not use a TTL type crystal oscillator with a TTL to PECL converter as the TTL signal conversion will generate significant jitter on the reference clock. The Clock Recovery unit (CRU) in the S/UNI-622-POS requires an external capacitor between the C0 and C1 pins to control the amount of "peaking" in the jitter transfer curve. The capacitor should be located as close as possible to the C0 and C1 pins in order to prevent noise from coupling into CRU. When the CRU is used in WAN mode (RTYPE bit in register 0x5E is set high), a 47nF non-polarized capacitor (ceramic 5% X7R or equivalent) must be connected between the C0 and C1 pins. The capacitor controls the amount of "peaking" in the jitter transfer response. It must be non-polarized as the capacitor may operate with a D.C. reverse-bias depending on process, voltage and temperature extremes. When the CRU is used in LAN mode (RTYPE bit in register 0x5E is set low), the C0 and C1 pins must be left floating. Please refer to the S/UNI-622-POS reference design (PMC-981070) for further recommendations. 13.18 System Interface DLL Operation The S/UNI-622-POS use digital delay lock loop (DLL) units to improve the output propagation timing on certain digital output pins. The TFCLK, RFCLK and PTCLK clock inputs each have a DLL to improve the timing on their associated interfaces. The DLL compensate for internal timing and output pad delays by adaptively delaying the input clock signal by approximately one clock period (1 UI) to create a new clock which controls the internal device logic. A side effect is that the DLL units imposes a minimum clock rate on each of the clock signals. For certain operation modes, such as 19.44MHz OC3 clocking on PTCLK, the DLL is bypassed. When the S/UNI-622-POS is reset, the DLL units find the initial delay lock. This process may take up to 3100 clock cycles to identify the lock position. During this intial lock period, device interface timing will not meet the timing specifications listed in A.C. Timing section. The TCA/TPA pin is held low when the TFCLK DLL is finding lock. If the clock inputs are not stable during this period (for instance, a clock is generated using an external PLL), the S/UNI-622-POS
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should be held in reset until the clocks are stable or the DLL should be reset using software control. The RFCLK, TFCLK and PTCLK DLL software resets are performed by writing 0x00 to registers 0x96, 0x9A and 0x9E respectively. When resetting the RFCLK or TFCLK DLL units, the associated FIFOs in the RXCP, RXFP, TXCP and RXCP must also be reset using the their FIFORST register bits. The RUN register bit is set high when the DLL finds lock after a system or software reset. The DLL units are sensitive to jitter on the clock inputs. The reason is that the DLL must track the changes in clock edges cause by changes in clock frequency, temperature, voltage and jitter. While the DLL may tolerate up to 0.4UIpp of clock jitter without losing phase lock, the output timing may degrade with excessive input jitter. Therefore, the high frequency clock jitter (above 1 MHz) should be less than value specified by the A.C. Timing section.
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14 FUNCTIONAL TIMING All functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the S/UNI-622POS registers are set to their default states). 14.1 Parallel Line Interface The In Frame Declaration Timing diagram (Figure 38) illustrates the declaration of the in-frame state by the SUNI-622-POS when processing a 77.76 Mbyte/s STS-12c/STM-4-4c stream on PIN[7:0]. An upstream serial-to-parallel converter indicates the location of the SONET/SDH frame using the FPIN input. The frame verification is initialized by a pulse on FPIN when the SUNI-622-POS is out of frame. The in-frame state is declared if the framing pattern is observed in the correct byte positions in the following frame, and in the intervening period (125 us) no additional pulse were present of FPIN. The SUNI-622-POS ignores pulses of FPIN while in frame. The algorithm results in a maximum average reframe time of 250 us in the absence of mimic framing patterns. Figure 38: In Frame Declaration Timing
PICLK PIN[7:0] FPIN OOF A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 A1 A2 A2 A2 Z0 Z0 Z0
125 us Between Framing Pattern Occurrences
The Out of Frame Declaration Timing diagram (Figure 39) illustrates the declaration of out of frame for a STS-12c stream. The framing pattern is a 196bit pattern that repeats once per frame. For the purposes of OOF declaration, the framing pattern may be modified using the ALGO2 bit in the RSOP Control register. Out of frame is declared when one or more errors are detected in this pattern for four consecutive frames as illustrated. In the presence of random data, out of frame will normally be declared within 500 us.
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Figure 39: Out of Frame Declaration Timing
PICLK PIN[7:0] OOF
Errored A1/A2 Pattern Errored A1/A2 Pattern Four Consecutive Frames Containing Framing Pattern Errors Errored A1/A2 Pattern Errored A1/A2 Pattern
A1 A1
A1
A2 A2 A2
A1 A1
A1 A2 A2 A2
A1 A1
A1 A2 A2 A2
A2
A2
A2
J0
Z0
Z0
The Parallel Transmit Timing diagram (Figure 40) illustrates the S/UNI-622-POS transmit STS-12c data stream on the parallel interface. The FPOUT signal marks the SONET/SDH frame alignment on the POUT[7:0] bus. FPOUT pulses high during the first synchronous payload envelope byte after the J0/Z0 bytes. Figure 40: Parallel Transmit Interface Timing
PTCLK POUT[7:0] FPOUT A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 A1 A2 A2 A2 Z0 Z0 Z0
125 us Between Framing Pattern Occurrences
14.2 ATM UTOPIA Level 2 System Interface The ATM UTOPIA Level 2 System Interface is compatible with the UTOPIA Level 2 specification (see References). The S/UNI-622-POS only supports the 16-bit mode of operation. The Transmit UTOPIA Level 2 System Interface Timing diagram (Figure 41) illustrates the operation of the system side transmit FIFO interface. Assertion of the transmit cell available output, TCA, indicates that there is space available in the transmit FIFO for at least one ATM cell structure. Deassertion of TCA occurs when the FIFO is filled with the number of ATM cells indicated by the register bits FIFODP[1:0]. If the TCA is configured to deassert early before the FIFO is truly full, the FIFO will accept additional cells even if TCA is inactive. At any time, if the upstream does not have a word to write, it must deassert TENB. As well, the TCA may be configured to deassert after the last word of a cell is written into the FIFO (FIFO is full) or as the cell is being written into the FIFO (FIFO is near full). In addition, the register bit TCAINV can be used to invert the polarity of TCA.
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TSOC must be high during the first word of the ATM cell structure and must be present for the start of each cell. When TSOC is asserted and the previous word transfer was not the end of an ATM cell structure, the system interface realigns itself to the new timing, and the previous partially transferred cell is dropped. Figure 41: Transmit UTOPIA Level 2 System Interface Timing
TFCLK TENB TDAT[15:0] TPRTY TSOC TCA W1 W2 W3 W23 W24 W25 W26 W27 W1 W2
The Receive UTOPIA Level 2 System Interface Timing diagram (Figure 42) illustrates the operation of the system side receive interface. The RXCP indicates that a cell is available by asserting the receive cell available output RCA. RCA remains high until the receive FIFO is empty. After RCA is deasserted, it remains low for a minimum of one RFCLK clock cycle and can then reassert to indicate that there are additional cells available in the FIFO. At any time, the downstream reader can throttle back the reception of words by deasserting RENB. The RDAT[15:0], RPRTY and RSOC signals tri-state when RENB is sampled deasserted. RSOC is high during the first word of the cell and is present for each cell. Figure 42: Receive UTOPIA Level 2 System Interface Timing
RFCLK RENB RDAT[15:0] RPRTY RSOC RCA W1 W2 W3 W23 W24 W25 W26 W27 W1 W2
14.3 ATM UTOPIA Level 3 System Interface The ATM UTOPIA Level 3 System Interface is compatible with the UTOPIA Level 3 specification (see References). The S/UNI-622-POS only supports the 8-bit mode of operation.
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The Transmit UTOPIA Level 3 System Interface Timing diagram (Figure 43) illustrates the operation of the system side transmit FIFO interface. Assertion of the transmit cell available output, TCA, indicates that there is space available in the transmit FIFO for at least one ATM cell structure. Deassertion of TCA occurs when the FIFO is filled with the number of ATM cells indicated by the register bits FIFODP[1:0]. If the TCA is configured to deassert early before the FIFO is truly full, the FIFO will accept additional cells even if TCA is inactive. At any time, if the upstream does not have a byte to write, it must deassert TENB. When TCA desserts, it will do so within 4 clocks cycles before the last byte of the cell. TSOC must be high during the first byte of the ATM cell structure and must be present for the start of each cell. Thus, TSOC will mark the H1 byte. When TSOC is asserted and the previous byte transferred was not the end of an ATM cell structure, the system interface realigns itself to the new timing, and the previous partially transferred cell is dropped. Figure 43: Transmit UTOPIA Level 3 System Interface Timing
TFCLK TENB TDAT[7:0] TPRTY TSOP TCA B1 B2 B3 B4 B49 B50 B51 B52 B53 B54 B1 B2
The Receive UTOPIA Level 3 System Interface Timing diagram (Figure 44) illustrates the operation of the system side receive interface. Unlike traditional UTOPIA interfaces, the SUNI-622-POS controls the bus. Because the bus is point to point, the SUNI-622-POS pushes received data to the downstream reader. As well, the control of RENB is pipelined to improve the speed of the interface. When a cell is available, the RVAL signal is asserted and the first byte of the cell appears on the RDAT[7:0] bus when RENB is low. The first byte of the structure is marked with RSOC being set high. Thus, RSOC will identify the H1 byte. The downstream reader may control the flow of data using RENB. If RENB is sampled low on the rising edge of RFCLK, the data on RDAT[7:0], RVAL and RSOC signals will be updated on the next rising edge of RFCLK. When RENB is sampled high on the rising edge of RFCLK, the data on RDAT[7:0], RVAL and RSOC will not change on the next rising edge of RFCLK. RENB must be low for at least 3 RFCLK clock cycles before RVAL will assert for the first byte of the first ATM cell.
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After the end of a cell, the SUNI-622-POS will keep the RVAL signal high and mark the first byte of the next cell with RSOC asserted if the receive FIFO contained more than one cell. Figure 44: Receive UTOPIA Level 3 System Interface Timing
RFCLK RENB RDAT[7:0] RPRTY RVAL RSOC B1 B2 B3 B50 B51 B52 B53 B54 B1 B2 B3
14.4 Packet over SONET/SDH (POS) Level 2 System Interface The Packet over SONET/SDH (POS) System Interface is compatible with the POS-PHY Level 2 specification (see References). The S/UNI-622-POS supports the byte level and packet level transfer modes of POS-PHY. The Transmit POS Level 2 System Interface Timing diagram (Figure 45) illustrates the operation of the system side transmit FIFO interface. Assertion of the transmit packet available output, TPA, indicates that there is space available in the transmit FIFO. Deassertion of TPA occurs when the FIFO is filled to the depth indicated by the register TPAHWM[7:0]. The exact octet that triggers the deassertion of TPA depends on the particular timing relationship between the internal SONET/SDH clock and TFCLK, and for that reason is not precise. However the TXFP is always conservative. Thus, when TPA deasserts with no more than TPAHWM[7:0] bytes in the FIFO remains. If TPA is asserted and the upstream is ready to write a byte, the upstream device should assert TENB. At any time, if the upstream does not have a word to write, it must deassert TENB. In addition, the register bit TPAINV can be used to invert the meaning of TPA. TSOP must be high during the first word of the packet and must be present for the start of each packet. TEOP must be high during the last packet word/byte transferred. During a packet transfer, every word must be composed of two bytes and TMOD shall be low. TMOD is used to during the last word of the packet transfer to determine if the word is composed of one or two bytes. It is legal to assert TSOP and TEOP at the same time. This case occurs when a 1byte or a 2-byte packet is transferred. When TSOP is asserted and the previous word transfer was not marked with TEOP, the system interface realigns itself to the new timing, and the previous packet is aborted.
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Figure 45: Transmit POS Level 2 System Interface Timing
TFCLK TENB TDAT[15:0] TPRTY TSOP TEOP TMOD TERR TPA B1,B2 B3,B4 B5,B6 B7,B8 B37,B38 B39,B40 B41,B42 B43,B44 B45 B1,B2 B3,B4
The Receive POS Level 2 System Interface Timing diagram (Figure 46) illustrates the operation of the system side receive interface. The RXFP indicates that a packet is available by asserting the receive packet available output RPA. RPA remains high until the receive FIFO is empty. After RPA is deasserted, it remains low for a minimum of one RFCLK clock cycle and then can assert to indicate that there are additional packets available in the FIFO. At any time, the downstream reader can throttle back the reception of words by deasserting RENB. RSOP is high during the first word of the packet. REOP is high during the last packet word. During a packet transfer every word is composed of two bytes. RMOD is used during the last word of the packet transfer to determine if the last word is composed of one or two bytes. It is legal to assert RSOP and REOP at the same time. This case occurs when a 1-byte or a 2-byte packet is transferred. Packets that were subject to an error (aborted, length violation, FIFO overrun, etc) will be marked by RERR high during the last word transfer. When a packet with less than 6 bytes arrives (from the line side), the receive packet available signal (RPA) may assert before data is available. In this condition, RPA will assert between 1 to 3 RFCLK clock cycles before the data is available and will remain asserted for 1 to 3 RFCLK clock cycles. When the Link Layer device attempts to read the packet by asserting read enable (RENB), it may find that there is no valid data available (receive data valid signal (RVAL) remains de-asserted). RPA will correctly assert again later when data is available. At this time the RVAL signal will be asserted indicating valid data. With packets greater than 6 bytes, the RPA signal will assert, de-assert and then reassert 1 to 3 RFCLK cycles later (same as the above case with packets less than 6 bytes). However, if the Link layer device attempts to read the packet on
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the basis of the first occurrence of RPA, it will read valid data (RVAL will be asserted), even if RPA may be de-asserted. This early assertion of RPA will not cause any data corruption if RVAL is used to qualify the data that is read. It is recommended that RVAL always be used to qualify receive data. The operation of RPA may cause a slight reduction bandwidth on receive side of the POS-PHY interface. However, since there is ample bandwidth on the POS-PHY interface there will be no impact on performance of functionality. During the transfer of a packet, valid data is marked by RVAL high. If the FIFO under-runs, or if REOP is encountered, the RXFP will de-assert RVAL to halt the transfer, and the link layer device must deassert RENB. A new transfer may then be started by asserting RENB when RPA indicates that more packet data is available. Figure 46: Receive POS Level 2 System Interface Timing
RFCLK RENB RDAT[15:0] RPRTY RVAL RSOP REOP RMOD RERR RPA B1,B2 B3,B4 B5,B6 B7,B8 B37,B3 B39,B4 B41 B1,B2 B3,B4
The receive POS-PHY Level 2 interface cannot support full bandwidth with arbitrarily small consecutive packets. In general, the minimum consecutive packet size the interface can transfer without overruning the receive FIFO in the TXFP is a function of how quickly the downstream logic reselects the S/UNI-622POS after an end of packet is transferred on the bus. If the number of cycles between packet transfers (that is, the number of RFCLK cycles between RVAL going low, RENB deasserting and then reasserting) is keep small, the minimum full-bandwidth packet size can be as low as 15 to 20 bytes. 14.5 Packet over SONET/SDH (POS) Level 3 System Interface The Packet over SONET/SDH (POS) Level 3 System Interface is compatible with the POS-PHY Level 3 specification (see References). The S/UNI-622-POS only supports the 8-bit mode of operation.
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The Transmit POS Level 3 System Interface Timing diagram (Figure 47) illustrates the operation of the system side transmit FIFO interface. Assertion of the transmit packet available output, TPA, indicates that there is space available in the transmit FIFO. Deassertion of TPA occurs when the FIFO is filled to the depth indicated by the register TPAHWM[7:0]. The exact octet that triggers the deassertion of TPA depends on the particular timing relationship between the internal SONET/SDH clock and TFCLK, and for that reason is not precise. However the TXFP is always conservative. Thus, when TPA deasserts with no more than TPAHWM[7:0] bytes in the FIFO remains. If TPA is asserted and the upstream is ready to write a byte, the upstream device should assert TENB. At any time, if the upstream does not have a byte to write, it must deassert TENB. In addition, the register bit TPAINV can be used to invert the meaning of TPA. TSOP must be high during the first byte of each packet. TEOP must be high during the last byte of the packet. It is legal to assert TSOP and TEOP at the same time. This case occurs when a one byte packet is transferred. When TSOP is asserted and the previous byte transfer was not marked with TEOP, the system interface realigns itself to the new timing, and the previous packet is marked to be aborted. When a packet with an odd number of bytes is transferred, the TENB signal must be deasserted for at least one clock cycle after TEOP is asserted (last byte of the packet is written into the FIFO). Transferring back-to-back packets (without deasserting TENB between the TEOP and TSOP) with odd number of bytes will cause the system interface to malfunction. Figure 47: Transmit POS Level 3 System Interface Timing
TFCLK TENB TDAT[15:0] TPRTY TSOP TEOP TMOD TERR TPA B1,B2 B3,B4 B5,B6 B7,B8 B37,B38 B39,B40 B41,B42 B43,B44 B45 B1,B2 B3,B4
The Receive POS Level 3 System Interface Timing diagram (Figure 48) illustrates the operation of the system side receive interface. Unlike POS Level 2 interfaces, the SUNI-622-POS controls the bus. Because the bus is point to
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point, the SUNI-622-POS pushes received data to the downstream reader. As well, the control of RENB is pipelined to improve the speed of the interface. When a cell is available, the RVAL signal is asserted and the first byte of the packet appears on the RDAT[7:0] bus when RENB is low. Thus, the RSOP signal marks the first byte of the packet. The downstream reader may control the flow of data using RENB. If RENB is sampled low on the rising edge of RFCLK, the data on RDAT[7:0], RVAL and RSOP signals will be updated on the next rising edge of RFCLK. When RENB is sampled high on the rising edge of RFCLK, the data on RDAT[7:0], RVAL and RSOP will not change on the next rising edge of RFCLK. RENB must be low for at least 3 RFCLK clock cycles before RVAL will assert for the first byte of the first packet. At the end of a packet, the SUNI-622-POS will keep the RVAL signal high and mark the first byte of the next packet if the receive FIFO contained more than one packet. It is legal to assert RSOP and REOP during the first byte of the packet to transfer a 1-byte packet. Packets that were subject to an error (aborted, length violation, FIFO overrun, etc) will be marked by RERR set high during the last byte of the transfer (when REOP is set high). Figure 48: Receive POS Level 3 System Interface Timing
RFCLK RENB RDAT[7:0] RPRTY RVAL RSOP REOP RERR B1 B2 B3 B4 B43 B44 B45 B46 B47 B1 B2 B3
The receive POS-PHY Level 3 interface cannot support full bandwidth with arbitrarily small consecutive packets. The Level 3 interface relies on an internal Level 2 interface which restricts the bandwidth on the Level 3 interface. In general, the Level 3 interface can support 15 byte packets consecutively fullbandwidth without the FIFO in the TXFP overruning. 14.6 Section and Line Data Communication Channels The SUNI-622-POS provides access to both Line and Section Data Communications Channels (DCC). Both channels are accessed using the serial
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interface pins RSD, RLD, TSD and TLD and their clocks RSDCLK, RLDCLK, TSDCLK and TLDCLK respectively. The Transport Overhead Data Link Clock and Data Extraction Timing diagram (Figure 49) shows the relationship between the RSD and RLD serial data outputs and their associated clocks, RSDCLK and RLDCLK. RSDCLK is a 216 kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate. RLDCLK is a 2.16 MHz, 67%(high)/33%(low) duty cycle clock that is gapped to produce a 576 kHz nominal rate. RSD is updated on the falling edge of RSDCLK. RLD is updated on the falling edge of RLDCLK. The D1-D3, and D4D12 bytes shifted out of the S/UNI-622-POS in the frame shown are extracted from the corresponding transport overhead channels in the previous frame. Figure 49: Transport Overhead Data Link Clock and Data Extraction
125 MICROSECONDS
RSDCLK RSD RLDCLK RLD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
APPROX. 2MHZ CLOCK BURST
RLDCLK RLD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
The Transport Overhead Data Link Clock and Data Insertion diagram (Figure 50) shows the relationship between the TSD and TLD serial data inputs, and their associated clock TSDCLK and TLDCLK respectively. TSDCLK is a 216 kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate. TLDCLK is a 2.16 MHz, 67%(high)/33%(low) duty cycle clock that is gapped to produce a 576 kHz nominal rate. TSD is sampled on the rising edge of TSDCLK. TLD is sampled on the rising edge of TLDCLK. The D1-D3, and D4-D12 bytes shifted in to the S/UNI-622-POS in the frame shown are inserted in the corresponding transport overhead channels in the next frame.
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Figure 50: Transport Overhead Data Link Clock and Data Insertion
125 MICROSECONDS
TSDCLK TSD TLDCLK TLD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
APPROX. 2MHZ CLOCK BURST
TLDCLK TLD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
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15 ABSOLUTE MAXIMUM RATINGS Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Table 18: Absolute Maximum Ratings Ambient Temperature under Bias Storage Temperature Supply Voltage Bias Voltage (VBIAS) Voltage on PECL Pin Voltage on 3.3V Tolerant Digital Pin Voltage on 5.0V Tolerant Digital Pin Static Discharge Voltage Latch-Up Current per Pin DC Input Current Lead Temperature Absolute Maximum Junction Temperature -40C to +85C -40C to +125C -0.3V to +4.6V (VDD - .3) to +5.5V -0.3V to VPBIAS+0.3V -0.3V to VVDD+0.3V -0.3V to VVBIAS+0.3V 1000 V 100 mA 20 mA +230C +150C
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16 D.C. CHARACTERISTICS
TA = -40C to +85C, VDD = 3.3V 10%, VAVD = 3.3V 5%, VDD < VVBIAS < 5.5V (Typical Conditions: TA = 25C, VDD = 3.3V, VAVD = 3.3V, VBIAS = 5V)
Table 19: D.C Characteristics Symbol VDD BIAS VIL VIH Parameter Power Supply 5V Tolerant Bias Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage Min 2.97 VDD 0 2.0 Typ 3.3 5.0 1.2 1.2 Max 3.63 5.5 0.8 Units Conditions Volts Volts Volts Volts Guaranteed Input Low voltage. Guaranteed Input High voltage. Guaranteed output Low voltage at VDD=2.97V and IOL=maximum rated for pad. Guaranteed output High voltage at VDD=2.97V and IOH=maximum rated current for pad. Applies to RSTB and TRSTB only. Applies to RSTB and TRSTB only. Applies to RSTB and TRSTB only. VPECL = 5.0V or 3.3V See note 4. VPECL = 5.0V or 3.3V See note 4. VPECL = 5.0V or 3.3V See note 4.
VOL
0.2
0.4
Volts
VOH
Output or Bidirectional High Voltage
2.4
2.6
Volts
VT+ VTVTH
VPECLI+ VPECLIVPECLIC
Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage Input PECL High Voltage Input PECL Low Voltage Input PECL Common Mode Voltage
2.0 0.8 0.3
Volts Volts Volts
VPECL - 1.165 VPECL - 1.810 VPECL - 1.490
VPECL - 0.955 VPECL 1.700 VPECL - 1.329
VPECL -0.880 VPECL - 1.470 VPECL - 1.180
Volts Volts Volts
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Symbol
Parameter
Min
VPECL - 0.880 VPECL - 1.620
Typ
VPECL - 0.955 VPECL - 1.705
Max
VPECL - 1.025 VPECL - 1.810
Units Conditions Volts Volts A A A A pF pF pF VPECL = 5.0V or 3.3V VPECL = 5.0V or 3.3V VIL = GND. Notes 1 and 3. VIH = VDD. Notes 1 and 3. VIL = GND. Notes 2 and 3. VIH = VDD. Notes 2 and 3. tA=25C, f = 1 MHz tA=25C, f = 1 MHz tA=25C, f = 1 MHz VDD = 3.63V, Outputs Unloaded VDD = 3.63V, Outputs Unloaded VDD = 3.63V, Outputs Unloaded
VPECLO+ Output PECL High Voltage VPCLO5- Output PECL Low Voltage IILPU Input Low Current IIHPU IIL IIH CIN COUT CIO IDDOP1 Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance Bi-directional Capacitance ATM Operation with CRU and CSU. ATM Operation with CSU, CRU bypassed ATM Operation with Parallel Line Interface (STS12c/STM-4-4c) POS Operation with CRU and CSU POS Operation with CSU, CRU bypassed. POS Operation with Parallel Line Interface (STS12c/STM-4-4c)
-100 -10 -10 -10
-50 0 0 0 5 5 5 490
-4 +10 +10 +10
580
mA
IDDOP2
440
550
mA
IDDOP3
402
510
mA
IDDOP4
530
620
mA
VDD = 3.63V, Outputs Unloaded VDD = 3.63V, Outputs Unloaded VDD = 3.63V, Outputs Unloaded
IDDOP5
490
600
mA
IDDOP6
440
550
mA
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Notes on D.C. Characteristics: 1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking); positive currents flow out of the device (sourcing). 4. The PECL inputs derive the common mode voltage from the differential signal pair. Differential input swings must be between 310mV and 1000mV for proper error-free operation. Specified maximum and minimun PECL input levels must be respected during normal operation.
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17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
(TA = -40C to +85C, VDD = 3.3V 10%, VAVD = 3.3V 5%)
Table 20: Microprocessor Interface Read Access (Figure 51) Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to INTB High Figure 51: Microprocessor Interface Read Timing Min 10 5 10 10 5 0 5 70 20 50 Max Units ns ns ns ns ns ns ns ns ns ns
tSar A[8:0] tSalr tVl ALE tSlr (CSB+RDB) tHalr
tHar
tHlr tZinth
INTB tPrd D[7:0] tZrd VALID
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Notes on Microprocessor Interface Read Timing: 15. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 16. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 17. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 18. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, tSLR, and tHLR are not applicable. 19. Parameter tHAR is not applicable if address latching is used. 20. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 21. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 22. Output tri-state delay is the time in nanoseconds from the 1.4 Volt of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current.
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Table 21: Microprocessor Interface Write Access (Figure 52) Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 20 10 10 5 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns
Figure 52: Microprocessor Interface Write Timing
tSaw A[8:0] tSalw tVl ALE tSlw (CSB+WRB) D[7:0] tVwr tHalw
tHaw
tSdw tHdw VALID
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Notes on Microprocessor Interface Write Timing: 1 A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2 In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW , tHALW , tVL, tSLW , and tHLW are not applicable. 3 Parameter tHAW is not applicable if address latching is used. 4 When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5 When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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18 A.C. TIMING CHARACTERISTICS
(TA = -40C to +85C, VDD = 3.3V 10%, VAVD = 3.3V 5%)
18.1 System Reset Timing Table 22: RSTB Timing (Figure 53) Symbol tVRSTB Description RSTB Pulse Width Min 100 Max Units ns
Figure 53: RSTB Timing Diagram
tVrstb RSTB
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18.2 Parallel Line Interface Timing Table 23: Transmit Parallel Line Interface Timing (Figure 54) Symbol fPTCLK DPTCLK JPTCLK tPPOUT tPFPOUT fPTCLK DPTCLK tPPOUT tPFPOUT Description STS12c PTCLK Frequency STS12c PTCLK Duty Cycle STS12c PTCLK Peak to Peak Jitter (>1 MHz) STS12c PTCLK High to POUT[7:0] Valid STS12c PTCLK High to FPOUT Valid STS3c PTCLK Frequency STS3c PTCLK Duty Cycle STS3c PTCLK High to POUT[7:0] Valid STS3c PTCLK High to FPOUT Valid 40 1 1 1 1 Min 60 40 Max 77.76 60 1 7 7 19.44 60 20 20 Units MHz % ns ns ns MHz % ns ns
Figure 54: Transmit Parallel Line Interface Timing Diagram
PTCLK tPpout POUT[7:0] tPfpout POUT[7:0]1
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Table 24: Receive Parallel Line Interface Timing (Figure 55) Symbol fPICLK DPICLK tSPIN tHPIN tSFPIN tHFPIN fPICLK DPICLK tSPIN tHPIN tSFPIN tHFPIN Description STS-12c PICLK Frequency STS-12c PICLK Duty Cycle STS-12c PIN[7:0] Set-up time to TFCLK STS-12c PIN[7:0] Hold time to TFCLK STS-12c FPIN Set-up time to TFCLK STS-12c FPIN Hold time to TFCLK STS-3c PICLK Frequency STS-3c PICLK Duty Cycle STS-3c PIN[7:0] Set-up time to TFCLK STS-3c PIN[7:0] Hold time to TFCLK STS-3c FPIN Set-up time to TFCLK STS-3c FPIN Hold time to TFCLK 40 2.5 1 2.5 1 Min 40 2.5 1 2.5 1 19.44 60 Max 77.76 60 Units MHz % ns ns ns ns MHz % ns ns ns ns
Figure 55: Receive Parallel Line Interface Timing Diagram
PICLK tSpin PIN[7:0] tSfpin FPIN tHfpin tHpin
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18.3 Serial Line Interface Timing Table 25: Receive Serial Line Interface Timing (Figure 56) Symbol fRRCLK DRRCLK tSRXD tHRXD Description RRCLK Frequency RRCLK Duty Cycle RXD+/- Set-up time to RRCLK RXD+/- Hold time to RRCLK Min 1 45 Max 622.04 55 200 800 Units MHz % ps ps
Figure 56: Receive Serial Line Interface Timing Diagram
RRCLK tSrxd RXD+/tHrxd
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18.4 UTOPIA Level 2 System Interface Timing Table 26: Transmit UTOPIA Level 2 System Interface Timing (Figure 57) Symbol fTFCLK DTFCLK JTFCLK tSTENB tHTENB tSTDAT tHTDAT tSTPRTY tHTPRTY tSTSOC tHTSOC tPTCA Description TFCLK Frequency TFCLK Duty Cycle TFCLK Peak to Peak Jitter (> 1 MHz) TENB Set-up time to TFCLK TENB Hold time to TFCLK TDAT[15:0] Set-up time to TFCLK TDAT[15:0] Hold time to TFCLK TPRTY Set-up time to TFCLK TPRTY Hold time to TFCLK TSOC Set-up time to TFCLK TSOC Hold time to TFCLK TFCLK High to TCA Valid 2 0 2 0 2 0 2 0 1 8.5 Min 40 40 Max 50 60 1.4 Units MHz % ns ns ns ns ns ns ns ns ns ns
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Figure 57: Transmit UTOPIA Level 2 System Interface Timing Diagram
TFCLK tStenb TENB tStdat TDAT[15:0] tStprty TPRTY tStsoc TSOC tPtca TCA tHtsoc tHtprty tHtdat tHtenb
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PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Table 27: Receive UTOPIA Level 2 System Interface Timing (Figure 58) Symbol fRFCLK DRFCLK JRFCLK tSRENB tHRENB tPRDAT tZRDAT tZBRDAT tPRSOC tZRSOC tZBRSOC tPRPRTY tZRPRTY tZBRPRTY tPRCA Description RFCLK Frequency RFCLK Duty Cycle RFCLK Peak to Peak Jitter (> 1 MHz) RENB Set-up time to RFCLK RENB Hold time to RFCLK RFCLK High to RDAT[15:0] Valid RFCLK High to RDAT[15:0] Tri-state RFCLK High to RDAT[15:0] Driven RFCLK High to RSOC Valid RFCLK High to RSOC Tri-state RFCLK High to RSOC Driven RFCLK High to RPRTY Valid RFCLK High to RPRTY Tri-state RFCLK High to RPRTY Driven RFCLK High to RCA Valid 2 0 1 1 0 1 1 1 1 1 0 1 8.5 8 8 8 8 8 8 Min 40 40 Max 50 60 1.4 Units MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
406
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 58: Receive UTOPIA Level 2 System Interface Timing Diagram
RFCLK tSrenb RENB tPrdat RDAT[15:0] tPrprty RPRTY tPrsop RSOC tPrca RCA tHrenb
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
407
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
18.5 UTOPIA Level 3 System Interface Timing Table 28: Transmit UTOPIA Level 3 System Interface Timing (Figure 59) Symbol fTFCLK DTFCLK JTFCLK tSTENB tHTENB tSTDAT tHTDAT tSTPRTY tHTPRTY tSTSOC tHTSOC tPTCA Description TFCLK Frequency TFCLK Duty Cycle TFCLK Peak to Peak Jitter (> 1 MHz) TENB Set-up time to TFCLK TENB Hold time to TFCLK TDAT[7:0] Set-up time to TFCLK TDAT[7:0] Hold time to TFCLK TPRTY Set-up time to TFCLK TPRTY Hold time to TFCLK TSOC Set-up time to TFCLK TSOC Hold time to TFCLK TFCLK High to TCA Valid 2 0 2 0 2 0 2 0 1 5 Min 60 40 Max 100 60 1 Units MHz % ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
408
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 59: Transmit UTOPIA Level 3 System Interface Timing Diagram
TFCLK tStenb TENB tStdat TDAT[7:0] tStprty TPRTY tStsoc TSOC tPtca TCA tHtsoc tHtprty tHtdat tHtenb
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
409
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Table 29: Receive UTOPIA Level 3 System Interface Timing (Figure 60) Symbol fRFCLK DRFCLK JRFCLK tSRENB tHRENB tPRDAT tPRSOC tPRPRTY tPRVAL Description RFCLK Frequency RFCLK Duty Cycle RFCLK Peak to Peak Jitter (> 1 MHz) RENB Set-up time to RFCLK RENB Hold time to RFCLK RFCLK High to RDAT[7:0] Valid RFCLK High to RSOC Valid RFCLK High to RPRTY Valid RFCLK High to RVAL Valid 2 0 1 1 1 1 5 5 5 5 Min 60 40 Max 100 60 1 Units MHz % ns ns ns ns ns ns ns
Figure 60: Receive UTOPIA Level 3 System Interface Timing Diagram
RFCLK tSrenb RENB tPrdat RDAT[15:0] tPrprty RPRTY tPrsop RSOC tPrval RVAL tHrenb
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
410
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
18.6 POS Level 2 System Interface Timing Table 30: Transmit POS-PHY Level 2 System Interface Timing (Figure 61) Symbol fTFCLK DTFCLK JTFCLK tSTENB tHTENB tSTDAT tHTDAT tSTPRTY tHTPRTY tSTSOP tHTSOP tSTEOP tHTEOP tSTMOD tHTMOD tSTERR tHTERR tPTPA Description TFCLK Frequency TFCLK Duty Cycle TFCLK Peak to Peak Jitter (> 1 MHz) TENB Set-up time to TFCLK TENB Hold time to TFCLK TDAT[15:0] Set-up time to TFCLK TDAT[15:0] Hold time to TFCLK TPRTY Set-up time to TFCLK TPRTY Hold time to TFCLK TSOP Set-up time to TFCLK TSOP Hold time to TFCLK TEOP Set-up time to TFCLK TEOP Hold time to TFCLK TMOD Set-up time to TFCLK TMOD Hold time to TFCLK TERR Set-up time to TFCLK TERR Hold time to TFCLK TFCLK High to TPA Valid 2 0 2 0 2 0 2 0 2 0 2 0 2 0 1 8.5 Min 40 40 Max 50 60 1 Units MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
411
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 61: Transmit POS-PHY Level 2 System Interface Timing
TFCLK tStenb TENB tStdat TDAT[15:0] tStprty TPRTY tStmod TMOD tStsop TSOP tSteop TEOP tSterr TERR tPtpa TPA tHterr tHteop tHtsop tHtmod tHtprty tHtdat tHtenb
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
412
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Table 31: Receive POS-PHY Level 2 System Interface Timing (Figure 62) Symbol fRFCLK DRFCLK JRFCLK tSRENB tHRENB tPRDAT tZRDAT tZBRDAT tPRPRTY tZRPRTY tZBRPRTY tPRSOP tZRSOP tZBRSOP tPREOP tZREOP tZBREOP tPRMOD tZRMOD tZBRMOD tPRERR tZRERR tZBRERR tPRVAL tZRVAL tZBRVAL tPRPA Description RFCLK Frequency RFCLK Duty Cycle RFCLK Peak to Peak Jitter (> 1 MHz) RENB Set-up time to RFCLK RENB Hold time to RFCLK RFCLK High to RDAT[15:0] Valid RFCLK High to RDAT[15:0] Tri-state RFCLK High to RDAT[15:0] Driven RFCLK High to RPRTY Valid RFCLK High to RPRTY Tri-state RFCLK High to RPRTY Driven RFCLK High to RSOP Valid RFCLK High to RSOP Tri-state RFCLK High to RSOP Driven RFCLK High to REOP Valid RFCLK High to REOP Tri-state RFCLK High to REOP Driven RFCLK High to RMOD Valid RFCLK High to RMOD Tri-state RFCLK High to RMOD Driven RFCLK High to RERR Valid RFCLK High to RERR Tri-state RFCLK High to RERR Driven RFCLK High to RVAL Valid RFCLK High to RVAL Tri-state RFCLK High to RVAL Driven RFCLK High to RPA Valid 2 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 8.5 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Min 40 40 Max 50 60 1 Units MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
413
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 62: Receive POS-PHY Level 2 System Interface Timing
RFCLK tSrenb RENB tPrdat RDAT[15:0] tPrprty RPRTY tPrmod RMOD tPrsop RSOP tPreop REOP tPrerr RERR tPrval RVAL tPrpa RPA tHrenb
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
414
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
18.7 POS Level 3 System Interface Timing Table 32: Transmit POS-PHY Level 3 System Interface Timing (Figure 63) Symbol fTFCLK DTFCLK JTFCLK tSTENB tHTENB tSTDAT tHTDAT tSTPRTY tHTPRTY tSTSOP tHTSOP tSTEOP tHTEOP tSTERR tHTERR tPTPA Description TFCLK Frequency TFCLK Duty Cycle TFCLK Peak to Peak Jitter (> 1 MHz) TENB Set-up time to TFCLK TENB Hold time to TFCLK TDAT[7:0] Set-up time to TFCLK TDAT[7:0] Hold time to TFCLK TPRTY Set-up time to TFCLK TPRTY Hold time to TFCLK TSOP Set-up time to TFCLK TSOP Hold time to TFCLK TEOP Set-up time to TFCLK TEOP Hold time to TFCLK TERR Set-up time to TFCLK TERR Hold time to TFCLK TFCLK High to TPA Valid 2 0 2 0 2 0 2 0 2 0 2 0 1 5 Min 60 40 Max 100 60 1 Units MHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
415
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 63: Transmit POS-PHY Level 3 System Interface Timing
TFCLK tStenb TENB tStdat TDAT[7:0] tStprty TPRTY tStsop TSOP tSteop TEOP tSterr TERR tPtpa TPA tHterr tHteop tHtsop tHtprty tHtdat tHtenb
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
416
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Table 33: Receive POS-PHY Level 3 System Interface Timing (Figure 64) Symbol fRFCLK DRFCLK JRFCLK tSRENB tHRENB tPRDAT tPRPRTY tPRSOP tPREOP tPRERR tPRVAL Description RFCLK Frequency RFCLK Duty Cycle RFCLK Peak to Peak Jitter (> 1 MHz) RENB Set-up time to RFCLK RENB Hold time to RFCLK RFCLK High to RDAT[7:0] Valid RFCLK High to RPRTY Valid RFCLK High to RSOP Valid RFCLK High to REOP Valid RFCLK High to RERR Valid RFCLK High to RVAL Valid 2 0 1 1 1 1 1 1 5 5 5 5 5 5 Min 60 40 Max 100 60 1 Units MHz % ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
417
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Figure 64: Receive POS-PHY Level 3 System Interface Timing
RFCLK tSrenb RENB tPrdat RDAT[7:0] tPrprty RPRTY tPrsop RSOP tPreop REOP tPrerr RERR tPrval RVAL tHrenb
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
418
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
18.8 Transmit DCC Interface Timing Table 34: Transmit DCC Interface Timing (Figure 65) Symbol tSTLD tHTLD tSTSD tHTSD Description TLD Set-up time to TLDCLK TLD Hold time to TLDCLK TSD Set-up time to TSDCLK TSD Hold time to TSDCLK Min 25 25 25 25 Max Units ns ns ns ns
Figure 65: Transmit DCC Interface Timing
TLDCLK tStld TLD TSDCLK tStsd TSD tHtsd tHtld
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
419
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
18.9 Receive DCC Interface Timing Table 35: Receive DCC Interface Timing (Figure 66) Symbol tPRLD tPRSD Description RLDCLK low to RLD valid RSDCLK low to RSD valid Min -20 -20 Max 20 20 Units ns ns
Figure 66: Receive DCC Interface Timing
RLDCLK tPrld RLD RSDCLK tPrsd RSD
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
420
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
18.10 Clock and Frame Pulse Interface Timing Table 36: Clock and Frame Pulse Interface Timing (Figure 67) Symbol Description TCLK Frequency TCLK Duty Cycle RCLK Frequency RCLK Duty Cycle tSTFPI tHTFPI tPTFPO tPRFPO TFPI Set-up time to TCLK TFPI Hold time to TCLK TCLK High FPO Valid RCLK High FPO Valid 40 2.5 0 1 1 6 6 40 Min Max 77.76 60 77.76 60 Units MHz % MHz % ns ns ns ns
Figure 67: Clock and Frame Pulse Interface Timing
TCLK tStfpi TFPI tPtfpo TFPO RCLK tPrfpo RFPO tHtfpi
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
421
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
18.11 JTAG Test Port Timing Table 37: JTAG Port Interface (Figure 68) Symbol Description TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 25 25 25 25 2 100 50 Min Max 4 60 Units MHz % ns ns ns ns ns ns
Figure 68: JTAG Port Interface Timing
TCK tStdi TDI tStms TMS tPtdo TDO tVtrstb TRSTB tHtms tHtdi
Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
422
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. Notes on Output Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 50 pF load on the outputs. 3. Output tri-state delay is the time in nanoseconds from the 1.4 Volt of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
423
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
19 ORDERING AND THERMAL INFORMATION Table 38: Ordering Information
PART NO. PM5357-BI DESCRIPTION 304-pin Ball Grid Array (SBGA)
Table 39: Thermal Information
PART NO. PM5357-BI AMBIENT TEMPERATURE -40C to 85C Theta Ja 22 C/W Theta Jc 1 C/W
PM 5357-BI
30 28 26 24 22 20 18 16 14 12 10 Conv 100 200 Dense Board 300 400 500
JEDEC Board
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
424
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
20 MECHANICAL INFORMATION Figure 69: Mechanical Drawing 304 Pin Super Ball Grid Array (SBGA)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
425
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
426
PRODUCTION S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5
PMC-Sierra, Inc.
PM5357 S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998, 1999, 2000 PMC-Sierra, Inc. PMC-980911 (R5) ref PMC-980106 (R5) Issue date: June 2000
PMC-Sierra, Inc..
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7
604

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